发明授权
- 专利标题: Recessed gate transistor structure and method of forming the same
- 专利标题(中): 嵌入式晶体管结构及其形成方法
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申请号: US11560756申请日: 2006-11-16
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公开(公告)号: US07777258B2公开(公告)日: 2010-08-17
- 发明人: Min-Hee Cho , Ji-Young Kim
- 申请人: Min-Hee Cho , Ji-Young Kim
- 申请人地址: KR Suwon-si
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si
- 代理机构: Stanzione & Kim, LLP
- 优先权: KR2003-70924 20031013
- 主分类号: H01L27/108
- IPC分类号: H01L27/108 ; H01L29/94
摘要:
Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.