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    Method of forming dual gate dielectric layer
    1.
    发明授权
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US07439604B2

    公开(公告)日：2008-10-21

    申请号：US11616836

    申请日：2006-12-27

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L29/00

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

    摘要翻译： 半导体器件包括提高半导体器件的性能的双栅介质层。 半导体器件包括在半导体衬底上具有预定厚度的第一电介质层。 第一介电层形成在第一区域上。 半导体器件还包括具有高于第一介电层的介电常数的介电常数的第二电介质层。 第二介电层形成在第一区域和第二区域两者上。

    Recessed gate transistor structure and method of forming the same
    2.
    发明申请
    Recessed gate transistor structure and method of forming the same 有权
    嵌入式晶体管结构及其形成方法

    公开(公告)号：US20050079661A1

    公开(公告)日：2005-04-14

    申请号：US10963928

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L21/00 ,  H01L21/84

    CPC分类号： H01L29/66621 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7834

    摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    摘要翻译： 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后，形成源/漏区。

    Transistors including laterally extended active regions and methods of fabricating the same
    3.
    发明授权
    Transistors including laterally extended active regions and methods of fabricating the same 有权
    包括横向延伸的有源区的晶体管及其制造方法

    公开(公告)号：US07470588B2

    公开(公告)日：2008-12-30

    申请号：US11387029

    申请日：2006-03-22

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/823481 ,  H01L27/10876 ,  H01L29/78

    摘要： A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.

    摘要翻译： 晶体管包括衬底和设置在衬底中的隔离区。 隔离区域限定包括上部和下部有源区域的有源区域，上部有源区域具有第一宽度，而下部有源区域具有大于第一宽度的第二宽度。 绝缘栅电极延伸穿过上有源区并进入下有源区。 源极和漏极区域设置在绝缘栅电极的相应第一和第二侧上的有源区中。 绝缘栅电极可以包括设置在上有源区中的上栅电极和设置在下有源区中的下栅电极，其中下栅电极比上栅极电极宽。 描述相关的制造方法。

    Method of forming dual gate dielectric layer
    4.
    发明授权
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US07169681B2

    公开(公告)日：2007-01-30

    申请号：US10964170

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, but leaving this layer on a first region; and forming a second dielectric layer having a dielectric constant higher than that of the first dielectric layer, on the first and second regions.

    摘要翻译： 通过使用具有高介电常数的介电层，包括在半导体衬底上形成具有预定厚度的第一介质层，形成双栅介质层的方法提高了半导体器件的性能; 去除形成在第二区域上的第一介电层，但将该层留在第一区域上; 以及在所述第一和第二区域上形成具有高于所述第一介电层的介电常数的介电常数的第二电介质层。

    Recessed gate transistor structure and method of forming the same
    5.
    发明授权
    Recessed gate transistor structure and method of forming the same 有权
    嵌入式晶体管结构及其形成方法

    公开(公告)号：US07153745B2

    公开(公告)日：2006-12-26

    申请号：US10963928

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7834

    摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    摘要翻译： 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后，形成源/漏区。

    Recessed gate transistor structure and method of forming the same
    6.
    发明授权
    Recessed gate transistor structure and method of forming the same 有权
    嵌入式晶体管结构及其形成方法

    公开(公告)号：US07777258B2

    公开(公告)日：2010-08-17

    申请号：US11560756

    申请日：2006-11-16

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L29/66621 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7834

    摘要： Recessed gate transistor structures and methods for making the same prevent a short between a gate conductive layer formed on a non-active region and an active region by forming an insulation layer therebetween, even though a misalignment is generated in forming a gate. The method and structure reduce the capacitance between gates. The method includes forming a device isolation film for defining an active region and a non-active region, on a predetermined region of a semiconductor substrate. First and second insulation layers are formed on an entire face of the substrate. A recess is formed in a portion of the active region. A gate insulation layer is formed within the recess, and then a first gate conductive layer is formed within the recess. A second gate conductive layer is formed on the second insulation layer and the first gate conductive layer. Subsequently, source/drain regions are formed.

    摘要翻译： 嵌入栅极晶体管结构及其制造方法即使在形成栅极时产生不对准，也可以通过在其间形成绝缘层来防止形成在非有源区上的栅极导电层与有源区之间的短路。 该方法和结构降低了门之间的电容。 该方法包括在半导体衬底的预定区域上形成用于限定有源区和非有源区的器件隔离膜。 第一和第二绝缘层形成在基板的整个表面上。 在有源区域的一部分中形成凹部。 在凹部内形成栅极绝缘层，然后在凹部内形成第一栅极导电层。 第二栅极导电层形成在第二绝缘层和第一栅极导电层上。 随后，形成源/漏区。

    Method of forming dual gate dielectric layer
    7.
    发明申请
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US20070102767A1

    公开(公告)日：2007-05-10

    申请号：US11616836

    申请日：2006-12-27

    申请人： Min-Hee CHO ,  Ji-Young Kim

    发明人： Min-Hee CHO ,  Ji-Young Kim

    IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.

    摘要翻译： 半导体器件包括提高半导体器件的性能的双栅介质层。 半导体器件包括在半导体衬底上具有预定厚度的第一电介质层。 第一介电层形成在第一区域上。 半导体器件还包括具有高于第一介电层的介电常数的介电常数的第二电介质层。 第二介电层形成在第一区域和第二区域两者上。

    Method of forming dual gate dielectric layer
    8.
    发明申请
    Method of forming dual gate dielectric layer 有权
    形成双栅介电层的方法

    公开(公告)号：US20050282352A1

    公开(公告)日：2005-12-22

    申请号：US10964170

    申请日：2004-10-12

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8234

    CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823462

    摘要： A method of forming a dual gate dielectric layer increases a performance of a semiconductor device by using a dielectric layer having a high dielectric constant, including forming a first dielectric layer having a predetermined thickness on a semiconductor substrate; removing the first dielectric layer formed on a second region, but leaving this layer on a first region; and forming a second dielectric layer having a dielectric constant higher than that of the first dielectric layer, on the first and second regions.

    摘要翻译： 通过使用具有高介电常数的介电层，包括在半导体衬底上形成具有预定厚度的第一介质层，形成双栅介质层的方法提高了半导体器件的性能; 去除形成在第二区域上的第一介电层，但将该层留在第一区域上; 以及在所述第一和第二区域上形成具有高于所述第一介电层的介电常数的介电常数的第二电介质层。

    Transistors including laterally extended active regions and methods of fabricating the same
    9.
    发明申请
    Transistors including laterally extended active regions and methods of fabricating the same 有权
    包括横向延伸的有源区的晶体管及其制造方法

    公开(公告)号：US20070063270A1

    公开(公告)日：2007-03-22

    申请号：US11387029

    申请日：2006-03-22

    申请人： Min-Hee Cho ,  Ji-Young Kim

    发明人： Min-Hee Cho ,  Ji-Young Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L29/66621 ,  H01L21/823481 ,  H01L27/10876 ,  H01L29/78

    摘要： A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.

    摘要翻译： 晶体管包括衬底和设置在衬底中的隔离区。 隔离区域限定包括上部和下部有源区域的有源区域，上部有源区域具有第一宽度，而下部有源区域具有大于第一宽度的第二宽度。 绝缘栅电极延伸穿过上有源区并进入下有源区。 源极和漏极区域设置在绝缘栅电极的相应第一和第二侧上的有源区中。 绝缘栅电极可以包括设置在上有源区中的上栅电极和设置在下有源区中的下栅电极，其中下栅电极比上栅极电极宽。 描述相关的制造方法。