A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.