Invention Grant
- Patent Title: Method of mounting electronic components
- Patent Title (中): 安装电子元器件的方法
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Application No.: US11816177Application Date: 2006-09-22
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Publication No.: US07793413B2Publication Date: 2010-09-14
- Inventor: Tadahiko Sakai , Hideki Eifuku
- Applicant: Tadahiko Sakai , Hideki Eifuku
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Pearne & Gordon LLP
- Priority: JP2005-288107 20050930
- International Application: PCT/JP2006/319403 WO 20060922
- International Announcement: WO2007/043355 WO 20070419
- Main IPC: H05K3/34
- IPC: H05K3/34 ; H05K1/16

Abstract:
An electronic component mounting method for mounting a electronic component on a board, in which an Au bump provided at an electronic component is joined to a joining terminal formed on a board by using solder made of Sn or solder containing Sn and the electronic component is adhered to the board by means of thermosetting resin thereby to mount the electronic component on the board. The applied thermosetting resin is flown toward the outside by the lower surface of the electronic component, then a part of the solder particles contained within the thermosetting resin are made in contact with the side surfaces of the Au bumps which are heated to the temperature higher than the melting point of the solder and also another part of the solder particles are molten in a state of being sandwiched between the Au bumps and the electrodes. Thus, the diffusion of Sn into the Au bumps from the outside is promoted and so the density of Sn within the Au bumps can be increased. Further, the diffusion of Sn into the Au bump from a solder joining portion can be suppressed and so the generation of Kirkendall voids can be suppressed.
Public/Granted literature
- US20090205203A1 METHOD OF MOUNTING ELECTRONIC COMPONENTS Public/Granted day:2009-08-20
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