发明授权
- 专利标题： Functional block level clock-gating within a graphics processor
- 专利标题（中）： 图形处理器内的功能块级时钟门控
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申请号： US11614248申请日： 2006-12-21
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公开(公告)号： US07802118B1公开(公告)日： 2010-09-21
- 发明人: Karim M. Abdalla , Robert J. Hasslen, III
- 申请人： Karim M. Abdalla , Robert J. Hasslen, III
- 申请人地址： US CA Santa Clara
- 专利权人： Nvidia Corporation
- 当前专利权人： Nvidia Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Cooley LLP
- 主分类号： G06F1/32
- IPC分类号： G06F1/32
摘要：
An embodiment of the invention includes receiving an indicator of a flow of data associated with a graphics processing stage within a graphics pipeline of a graphics processor. A clock signal to a portion of the graphics processing stage is modified based on a status of the flow of data. The clock signal is received from a clock signal generator within the graphics processor.
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