发明授权
US07805627B2 Clock synchronization scheme for deskewing operations in a data interface
有权
时钟同步方案,用于数据接口中的歪斜操作
- 专利标题: Clock synchronization scheme for deskewing operations in a data interface
- 专利标题(中): 时钟同步方案,用于数据接口中的歪斜操作
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申请号: US11729627申请日: 2007-03-29
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公开(公告)号: US07805627B2公开(公告)日: 2010-09-28
- 发明人: Mamun Ur Rashid , Hing Y. To
- 申请人: Mamun Ur Rashid , Hing Y. To
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop, Pruner & Hu, P.C.
- 主分类号: G06F1/04
- IPC分类号: G06F1/04 ; G06F1/12 ; G06F1/14
摘要:
A technique includes providing transmitters that are each associated with a data bit line of a bus, and each transmitter is clocked by an associated transmit clock signal. The technique includes determining a baseline offset to apply to a base clock signal to synchronize the base clock signal to a source clock signal of a source that supplies data to the transmitters. For each transmitter, an associated phase offset is determined to compensate for an associated skew. The phase of each transmit clock signal is controlled based on the associated phase offset and the baseline offset.
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