发明授权
- 专利标题: Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten
- 专利标题(中): 沟通处理通信相邻的阶段和控制,以防止地址信息被覆盖
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申请号: US11517327申请日: 2006-09-08
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公开(公告)号: US07818546B2公开(公告)日: 2010-10-19
- 发明人: Shigehiro Asano , Takashi Yoshikawa
- 申请人: Shigehiro Asano , Takashi Yoshikawa
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- 优先权: JP2006-043182 20060220
- 主分类号: G06F9/00
- IPC分类号: G06F9/00 ; G06F7/38 ; G06F9/44 ; G06F13/00
摘要:
A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
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