Invention Grant
- Patent Title: Low area architecture in BCH decoder
- Patent Title (中): BCH解码器中的低域架构
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Application No.: US11613529Application Date: 2006-12-20
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Publication No.: US07823050B2Publication Date: 2010-10-26
- Inventor: Elyar E. Gasanov , Alexander Andreev , Ilya V. Neznanov , Pavel A. Panteleev , Sergei Gashkov
- Applicant: Elyar E. Gasanov , Alexander Andreev , Ilya V. Neznanov , Pavel A. Panteleev , Sergei Gashkov
- Applicant Address: US CA Milpitas
- Assignee: LSICorporation
- Current Assignee: LSICorporation
- Current Assignee Address: US CA Milpitas
- Agency: Luedeka, Neely & Graham, P.C.
- Main IPC: H03M13/00
- IPC: H03M13/00
Abstract:
An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X
Public/Granted literature
- US20080155381A1 Low Area Architecture in BCH Decoder Public/Granted day:2008-06-26
Information query
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