公开(公告)号：US08868890B2

公开(公告)日：2014-10-21

申请号：US13106119

申请日：2011-05-12

Applicant: Yurii S. Shutkin ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Andrey P. Sokolov ,  Pavel A. Panteleev

Inventor： Yurii S. Shutkin ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Andrey P. Sokolov ,  Pavel A. Panteleev

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/322 ,  G06F9/30054 ,  G06F9/30065

Abstract: An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface.

Abstract translation: 通常包括存储器和电路的装置被公开。 存储器可以被配置为存储多个指令。 每个指令通常包括相应的命令和相应的命令重复计数。 指令中的至少一个可以包括子过程调用。 电路可以被配置为（i）一次解码指令，以及（ii）在接口处呈现一系列命令。 序列（i）可以基于解码，并且（ii）在接口的连续命令之间可以没有延迟。

公开(公告)号：US08842784B2

公开(公告)日：2014-09-23

申请号：US13115359

申请日：2011-05-25

Applicant: Andrey P. Sokolov ,  Pavel A. Panteleev ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Yurii S. Shutkin

Inventor： Andrey P. Sokolov ,  Pavel A. Panteleev ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Yurii S. Shutkin

IPC: H03M13/03 ,  H03M13/00 ,  H03M13/39 ,  H03M13/29

CPC classification number: H03M13/296 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/6525 ,  H03M13/6544

Abstract: An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of load values corresponding to a trellis of a decoding process. The second circuit generally includes a plurality of calculation layers. The calculation layers may be configured to generate a plurality of maximum values in response to the load values. The third circuit may be configured to generate a plurality of L-values of the decoding process in response to the maximum values.

Abstract translation: 公开了一种具有第一电路，第二电路和第三电路的装置。 第一电路可以被配置为产生对应于解码处理格架的多个负载值。 第二电路通常包括多个计算层。 计算层可以被配置为响应于负载值产生多个最大值。 第三电路可以被配置为响应于最大值产生解码处理的多个L值。

公开(公告)号：US08621329B2

公开(公告)日：2013-12-31

申请号：US13044809

申请日：2011-03-10

Applicant: Pavel A. Panteleev ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Andrey P. Sokolov ,  Yurii S. Shutkin

Inventor： Pavel A. Panteleev ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Andrey P. Sokolov ,  Yurii S. Shutkin

IPC: H03M13/00

CPC classification number: H03M13/6516 ,  H03M13/152 ,  H03M13/1525 ,  H03M13/6561

Abstract: An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.

Abstract translation: 公开了一种通常具有端口，第一电路和第二电路的装置。 端口可以​​被配置为接收码字的当前长度。 当前长度可以小于设备被设计为解码的码字的最大长度。 第一电路可以被配置为并行计算（i）来自码字的中间综合征序列，以及（ii）基于当前长度的校正值序列。 第二电路可以被配置为通过用修正值修改中间综合征来生成特定数量的更新的综合征。 特定数字通常是码字的最大误差限制的两倍。

公开(公告)号：US20110239079A1

公开(公告)日：2011-09-29

申请号：US12894458

申请日：2010-09-30

Applicant: Andrey P. Sokolov ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Pavel A. Aliseychik ,  Pavel A. Panteleev

Inventor： Andrey P. Sokolov ,  Elyar E. Gasanov ,  Ilya V. Neznanov ,  Pavel A. Aliseychik ,  Pavel A. Panteleev

IPC: H03M13/27 ,  G06F11/10

CPC classification number: H03M13/2771 ,  H03M13/2767 ,  H03M13/6519 ,  H04L1/005 ,  H04L1/0066 ,  H04L1/0071

Abstract: A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.

Abstract translation: 公开了具有第一电路和存储器的电路。 第一电路可以被配置为（i）接收识别多个无线通信标准中的当前一个无线通信标准和码字大小的控制信号，并且（ii）生成与当前无线通信标准和 代码字大小。 每个表格通常具有多个索引。 每个时钟周期最多可以由第一个电路产生两个索引。 每个表通常包括turbo码交织器的置换表。 可以将存储器配置为存储表。

公开(公告)号：US20100281344A1

公开(公告)日：2010-11-04

申请号：US12612141

申请日：2009-11-04

Applicant: Elyar E. Gasanov ,  Andrey P. Sokolov ,  Pavel A. Panteleev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

Inventor： Elyar E. Gasanov ,  Andrey P. Sokolov ,  Pavel A. Panteleev ,  Ilya V. Neznanov ,  Pavel A. Aliseychik

IPC: H03M13/07 ,  G06F11/10

CPC classification number: H03M13/453 ,  H03M13/1515 ,  H03M13/154

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may (i) generate a decoded codeword by decoding a first codeword a plurality of times based on a respective plurality of erasure location vectors and (ii) assert a fail signal upon each failure of the decoding of the first codeword, the decoding comprising an error-and-erasure Reed-Solomon decoding. The second circuit may (i) generate a count of the assertions of the fail signal and (ii) generate the erasure location vectors based on (a) the count and (b) a plurality of reliability items corresponding to the first codeword.

Abstract translation: 公开了一种具有第一电路和第二电路的装置。 第一电路可以（i）通过基于相应的多个擦除位置向量多次解码第一码字来生成解码码字，以及（ii）在第一码字的解码失败时断言故障信号，解码 包括错误和擦除Reed-Solomon解码。 第二电路可以（i）产生故障信号的断言的计数，以及（ii）基于（a）计数和（b）与第一码字对应的多个可靠性项产生擦除位置向量。

公开(公告)号：US07401313B2

公开(公告)日：2008-07-15

申请号：US11258738

申请日：2005-10-26

Applicant: Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

Inventor： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

IPC: G06F17/50 ,  G06F7/00

CPC classification number: G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

Abstract: The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

Abstract translation: 本公开涉及一种用于将集成电路设计字段划分为具有用户可选择尺寸的多个拥塞矩形的方法和装置。 在设计字段内路由互连之前，为每个拥塞矩形估计路由拥塞值。 拥塞值存储在机器可读存储器中，并响应于设计领域内的线路更改而被更新。

公开(公告)号：US06637016B1

公开(公告)日：2003-10-21

申请号：US09841824

申请日：2001-04-25

Applicant: Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Ivan Pavisic ,  Aiguo Lu

Inventor： Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Ivan Pavisic ,  Aiguo Lu

IPC: G06F1750

CPC classification number: G06F17/5072

Abstract: A method for selectively placing cells of an application-specific integrated circuit on a substrate surface, including the steps of defining a grid covering a substrate surface, assigning cells to the grid to provide old x and y coordinates of the cells relative to the grid, grouping the cells by function to provide functional regions within the grid, determining a density map of the surface of the substrate in all the functional regions within the grid, determining free space of the grid on the surface of the substrate relative to the density map, and assigning new cells to the free space of the grid on the substrate surface to provide an application specific integrated circuit. Use of the method provides improved layout of an integrated circuit with minimal cell congestion or overlapping.

Abstract translation: 一种用于选择性地将专用集成电路的单元放置在衬底表面上的方法，包括以下步骤：限定覆盖衬底表面的栅格，将单元分配给栅格以提供单元相对于栅格的旧x和y坐标， 通过功能对细胞进行分组以在网格内提供功能区域，确定网格内所有功能区域中基底表面的密度图，确定基底表面上的网格相对于密度图的自由空间， 并将新的单元分配给衬底表面上的栅格的自由空间以提供专用集成电路。 该方法的使用提供了具有最小的信元拥塞或重叠的集成电路的改进布局。

公开(公告)号：US06543032B1

公开(公告)日：2003-04-01

申请号：US09678479

申请日：2000-10-02

Applicant: Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexander S. Podkolzin ,  Valery B. Kudryavtsev

Inventor： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexander S. Podkolzin ,  Valery B. Kudryavtsev

IPC: G06F1715

CPC classification number: G06F17/505

Abstract: Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.

Abstract translation: 提供了用于优化集成电路设计的系统和技术，其中在集成电路设计中识别关键区域，并且在临界区域中应用多个备选标识，以获得相应的多个结果。 然后，替代表示被识别为多个结果中的代表性表示，根据该结果，突发时间和定时中的至少一个被改进，并且基于指定的优先级来选择替代表示中的最佳替代表示来替换到临界区，所述优先级包括：（i ）选择基于减少违约时间; （ii）从基于时间改进保留细胞区域的替代表示中进行选择; 和（iii）如果所有替代表示增加单元格区域，则基于对时间递减和面积增量之间的关系的评估进行选择。

公开(公告)号：US06253363B1

公开(公告)日：2001-06-26

申请号：US09062218

申请日：1998-04-17

Applicant: Elyar E. Gasanov ,  Ranko Scepanovic ,  Pedja Raspopovic ,  Alexander E. Andreev

Inventor： Elyar E. Gasanov ,  Ranko Scepanovic ,  Pedja Raspopovic ,  Alexander E. Andreev

IPC: G06F1750

CPC classification number: G06F17/5077

Abstract: A method for routing a net on an integrated circuit device, said method comprising the steps of creating a list of basis elements of the net, said basis elements being defined by a predetermined size limitation, determining a complexity value for each basis element as a function of the distance between pins in the basis element, forming a hypertree for the net as a function of complexity values of basis elements so determined, and routing the net as a function of the hypertree.

Abstract translation: 一种用于在集成电路设备上路由网络的方法，所述方法包括以下步骤：创建网络的基本元素的列表，所述基本元素由预定大小限制定义，将每个基元元素的复杂度值确定为函数 在基元中的引脚之间的距离，形成网的强度作为如此确定的基本元素的复杂度的函数，并且将网作为强调函数来布线。

公开(公告)号：US09319181B2

公开(公告)日：2016-04-19

申请号：US13291285

申请日：2011-11-08

Applicant: Andrey P. Sokolov ,  Elyar E. Gasanov ,  Pavel A. Panteleev ,  Ilya V. Neznanov ,  Yurii S. Shutkin

Inventor： Andrey P. Sokolov ,  Elyar E. Gasanov ,  Pavel A. Panteleev ,  Ilya V. Neznanov ,  Yurii S. Shutkin

IPC: H03K9/00 ,  H04B1/38 ,  H04L1/00

CPC classification number: H04L1/0054 ,  H04L1/0052 ,  H04L1/0059 ,  H04L1/0066

Abstract: A method of parallel decoding for a plurality of communications standards generally including steps (A) to (C) is disclosed. Step (A) may receive a plurality of first words, at least two of the first words generally have a different length than each other. Step (B) may parse the first words into a plurality of memories. Step (C) may generate a plurality of second words by decoding the first words using a plurality of decoders. The decoders generally operate in parallel. The decoding of at least one of the first words may be performed by at least two of the decoders. The decoding is generally based on a signal that identifies a current one of the communications standards used to transfer the first words.

Abstract translation: 公开了通常包括步骤（A）至（C）的多个通信标准的并行解码方法。 步骤（A）可以接收多个第一单词，至少两个第一单词通常具有彼此不同的长度。 步骤（B）可以将第一个单词解析成多个存储器。 步骤（C）可以通过使用多个解码器对第一个字进行解码来生成多个第二字。 解码器通常并行运行。 至少一个第一个字的解码可以由至少两个解码器执行。 解码通常基于识别用于传送第一个字的通信标准中的当前一个的信号。