发明授权
- 专利标题： Test pad design for reducing the effect of contact resistances
- 专利标题（中）： 测试垫设计，以减少接触电阻的影响
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申请号： US12196531申请日： 2008-08-22
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公开(公告)号： US07825678B2公开(公告)日： 2010-11-02
- 发明人: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- 申请人： Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： G01R31/02
- IPC分类号： G01R31/02
摘要：
An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
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