发明授权
US07833895B2 TSVS having chemically exposed TSV tips for integrated circuit devices
有权
TSVS具有用于集成电路器件的化学暴露的TSV尖端
- 专利标题: TSVS having chemically exposed TSV tips for integrated circuit devices
- 专利标题(中): TSVS具有用于集成电路器件的化学暴露的TSV尖端
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申请号: US12463282申请日: 2009-05-08
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公开(公告)号: US07833895B2公开(公告)日: 2010-11-16
- 发明人: Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
- 申请人: Thomas D. Bonifield , Brian E. Goodlin , Mona M. Eissa
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Yingsheng Tung; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
A method for fabricating ICs including via-first through substrate vias (TSVs) and ICs and electronic assemblies therefrom. A substrate having a substrate thickness including a top semiconductor surface and a bottom surface is provided including at least one embedded TSV including a dielectric liner and an electrically conductive filler material formed on the dielectric liner. A portion of the bottom surface of the substrate is mechanically removed to approach but not reach the embedded TSV tip. A protective substrate layer having a protective layer thickness remains over the tip of the embedded TSV after the mechanical removing. Chemical etching exclusive of mechanical etching for removing the protective substrate layer is used form an integral TSV tip that has an exposed tip portion that generally protrudes from the bottom surface of the substrate. The chemical etching is generally a three step chemical etch.
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