发明授权
US07853636B2 Digital signal processing circuit having a pattern detector circuit for convergent rounding
有权
具有用于收敛四舍五入的图案检测器电路的数字信号处理电路
- 专利标题： Digital signal processing circuit having a pattern detector circuit for convergent rounding
- 专利标题（中）： 具有用于收敛四舍五入的图案检测器电路的数字信号处理电路
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申请号： US11432847申请日： 2006-05-12
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公开(公告)号： US07853636B2公开(公告)日： 2010-12-14
- 发明人: Bernard J. New , Jennifer Wong , James M. Simkins , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
- 申请人： Bernard J. New , Jennifer Wong , James M. Simkins , Alvin Y. Ching , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Thomas George
- 主分类号： G06F7/499
- IPC分类号： G06F7/499
摘要：
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.
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