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31 条记录 (耗时 0.022 秒)

    Method and system for configuring an integrated circuit
    4.
    发明授权
    Method and system for configuring an integrated circuit 有权
    用于配置集成电路的方法和系统

    公开(公告)号：US07314174B1

    公开(公告)日：2008-01-01

    申请号：US10970964

    申请日：2004-10-22

    申请人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    发明人： Vasisht Mantra Vadi ,  David P. Schultz ,  Steven P. Young ,  Jennifer Wong

    IPC分类号： G06K7/10 ,  G06K9/36 ,  G06K9/80

    CPC分类号： H03K19/177

    摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.

    摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。

    Efficient implementation of a bypassable flip-flop with a clock enable
    6.
    发明授权
    Efficient implementation of a bypassable flip-flop with a clock enable 有权
    高效实现具有时钟使能的旁路触发器

    公开(公告)号：US07129762B1

    公开(公告)日：2006-10-31

    申请号：US11059967

    申请日：2005-02-17

    申请人： Vasisht Mantra Vadi

    发明人： Vasisht Mantra Vadi

    IPC分类号： H03K3/12 ,  H03K3/289

    CPC分类号： H03K3/012 ,  H03K3/037

    摘要： A flip-flop circuit includes a flip-flop, a first pass gate, a second pass gate, and a third pass gate. The first pass gate has an input to receive an input signal, an output coupled to the flip-flop's data input, and a control terminal to receive a first control signal. The second pass gate has an input coupled to the flip-flop's data input, an output coupled to the circuit's output, and a control terminal to receive a second control signal. The third pass gate has an input coupled to the flip-flop's data output, an output coupled to the circuit's output, and a control terminal to receive a third control signal. The first, second, and third control signals may be generated in response to various logical combinations of a bypass signal and a clock enable signal.

    摘要翻译： 触发器电路包括触发器，第一通过栅极，第二栅极和第三栅极。 第一传输门具有用于接收输入信号的输入端，耦合到触发器数据输入端的输出端和用于接收第一控制信号的控制端子。 第二传输门具有耦合到触发器的数据输入，耦合到电路的输出的输出和用于接收第二控制信号的控制端的输入。 第三传输门具有耦合到触发器的数据输出的输入，耦合到电路的输出的输出以及用于接收第三控制信号的控制端。 可以响应于旁路信号和时钟使能信号的各种逻辑组合来产生第一，第二和第三控制信号。

    Clock multiplexing system
    7.
    发明授权
    Clock multiplexing system 有权
    时钟复用系统

    公开(公告)号：US07071756B1

    公开(公告)日：2006-07-04

    申请号：US10837329

    申请日：2004-04-30

    申请人： Vasisht Mantra Vadi ,  Steven P. Young

    发明人： Vasisht Mantra Vadi ,  Steven P. Young

    IPC分类号： G06F1/04 ,  H03K3/00

    CPC分类号： G06F1/04 ,  H03K17/005 ,  H03K17/693

    摘要： A clock control circuit in an integrated circuit for providing a differential clock signal to a differential clock tree. The clock control circuit includes: first differential multiplexers configured to select first outputs from the input clock signals; second differential multiplexers coupled to the first differential multiplexers and configured to select second outputs from the first outputs; loop back signal lines configured to feed back the second outputs to at least part of the input clock signals of the first differential multiplexers; and differential signal lines of the differential clock tree coupled to the second outputs.

    摘要翻译： 用于向差分时钟树提供差分时钟信号的集成电路中的时钟控制电路。 时钟控制电路包括：第一差分复用器，被配置为从输入时钟信号中选择第一输出; 第二差分多路复用器，耦合到所述第一差分多路复用器，并且被配置为从所述第一输出中选择第二输出; 配置为将所述第二输出反馈到所述第一差分多路复用器的输入时钟信号的至少一部分的环回信号线; 以及差分时钟树的差分信号线耦合到第二输出。

    Digital signal processing block having a wide multiplexer
    8.
    发明授权
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号：US07865542B2

    公开(公告)日：2011-01-04

    申请号：US11433120

    申请日：2006-05-12

    申请人： Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    发明人： Bernard J. New ,  Vasisht Mantra Vadi ,  Jennifer Wong ,  Alvin Y. Ching ,  John M. Thendean ,  Anna Wing Wah Wong ,  James M. Simkins

    IPC分类号： G06F7/38

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    摘要翻译： 一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

    Integrated circuit having embedded differential clock tree
    10.
    发明授权
    Integrated circuit having embedded differential clock tree 有权
    集成电路具有嵌入式差分时钟树

    公开(公告)号：US07759973B1

    公开(公告)日：2010-07-20

    申请号：US12174502

    申请日：2008-07-16

    申请人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    发明人： Vasisht Mantra Vadi ,  Steven P. Young ,  Atul V. Ghia ,  Adebabay M. Bekele ,  Suresh M. Menon

    IPC分类号： H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。