发明授权
- 专利标题: Caching in multicore and multiprocessor architectures
- 专利标题(中): 在多核和多处理器架构中进行缓存
-
申请号: US11754062申请日: 2007-05-25
-
公开(公告)号: US07853754B1公开(公告)日: 2010-12-14
- 发明人: Anant Agarwal , Ian R. Bratt , Matthew Mattina
- 申请人: Anant Agarwal , Ian R. Bratt , Matthew Mattina
- 申请人地址: US MA Westborough
- 专利权人: Tilera Corporation
- 当前专利权人: Tilera Corporation
- 当前专利权人地址: US MA Westborough
- 代理机构: Fish & Richardson P.C.
- 主分类号: G06F12/00
- IPC分类号: G06F12/00
摘要:
A multicore processor comprises a plurality of cache memories; a plurality of processor cores, each associated with one of the cache memories; one or more memory interfaces providing memory access paths from the cache memories to a main memory; and one or more directory controllers for respective portions of the main memory, each associated with corresponding storage for directory state. Each corresponding storage provides space for maintaining directory state for each memory line that is indicated as stored in at least one of the cache memories such that the space for maintaining directory state is independent of the size of the main memory.