发明授权
- 专利标题: Method for forming a trigger device for ESD protection circuit
- 专利标题(中): 形成ESD保护电路触发装置的方法
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申请号: US12565855申请日: 2009-09-24
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公开(公告)号: US07858469B1公开(公告)日: 2010-12-28
- 发明人: Jeffrey Watt , Irfan Rahim
- 申请人: Jeffrey Watt , Irfan Rahim
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Ward & Olivo LLP
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234
摘要:
The present invention is a trigger device useful, for example, in triggering an SCR in an ESD protection circuit. Illustratively, an NMOS trigger device comprises a gate and heavily doped P and N regions in a P-well on opposite sides of the gate. A first N type source/drain extension and a first P-type pocket region extend from the P region toward the N region with the pocket region located under the source/drain extension and extending under the gate. A second N-type source/drain extension and a second P-type pocket region extend from the N region toward the P region with the pocket region located under the source/drain extension and extending under the gate. Preferably, the gate itself is heavily doped so that one half of the gate on the side adjacent the heavily doped P region is also heavily doped with dopants of P-type conductivity and the other half of the gate on the side adjacent the heavily doped N region is also heavily doped with dopants of N-type conductivity. Doping the gate increases the threshold voltage by about one Volt due to an increase in the work function on the source side of the gate.
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