发明授权
- 专利标题: Method of measuring on-resistance in backside drain wafer
- 专利标题(中): 测量背面漏极晶片导通电阻的方法
-
申请号: US12325168申请日: 2008-11-29
-
公开(公告)号: US07859291B2公开(公告)日: 2010-12-28
- 发明人: Yeo-Hwang Kim
- 申请人: Yeo-Hwang Kim
- 申请人地址: KR Seoul
- 专利权人: Dongbu HiTek Co., Ltd.
- 当前专利权人: Dongbu HiTek Co., Ltd.
- 当前专利权人地址: KR Seoul
- 代理机构: Sherr & Vaughn, PLLC
- 优先权: KR10-2007-0124462 20071203
- 主分类号: G01R31/26
- IPC分类号: G01R31/26 ; H01L27/088
摘要:
A method of measuring on-resistance in a backside drain wafer includes providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer, and then forming a current flow path passing through the first and second MOS transistors, and then measuring a resistance between the sources of the first and second MOS transistors. Accordingly, an on-resistance in a backside drain wafer can be measured without using a chuck.
公开/授权文献
信息查询