发明授权
US07861014B2 System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
有权
用于将部分高速缓存行读取操作支持到存储器模块以减少存储器通道上的读取数据流量的系统
- 专利标题: System for supporting partial cache line read operations to a memory module to reduce read data traffic on a memory channel
- 专利标题(中): 用于将部分高速缓存行读取操作支持到存储器模块以减少存储器通道上的读取数据流量的系统
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申请号: US11848312申请日: 2007-08-31
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公开(公告)号: US07861014B2公开(公告)日: 2010-12-28
- 发明人: Kevin C. Gower , Warren E. Maule
- 申请人: Kevin C. Gower , Warren E. Maule
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Francis Lammes; Stephen J. Walder, Jr.; Diana R. Gerhardt
- 主分类号: G06F13/00
- IPC分类号: G06F13/00
摘要:
A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.
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