发明授权
- 专利标题: Fault tolerant time synchronization mechanism in a scaleable multi-processor computer
- 专利标题(中): 可扩展多处理器计算机中的容错时间同步机制
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申请号: US12140028申请日: 2008-06-16
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公开(公告)号: US07865758B2公开(公告)日: 2011-01-04
- 发明人: Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
- 申请人: Scott Barnett Swaney , Kenneth Lundy Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Yee & Associates, P.C.
- 代理商 Diana R. Gerhardt
- 主分类号: G06F1/12
- IPC分类号: G06F1/12
摘要:
Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.