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1.发明申请Method for Fault Tolerant Time Synchronization Mechanism in a Large Scaleable Multi-Processor Computer 失效大型可扩展多处理器计算机中容错时间同步机制的方法公开(公告)号：US20080215906A1
公开(公告)日：2008-09-04
申请号：US12116652
申请日：2008-05-07
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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2.发明申请Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-Processor Computer 失效可扩展多处理器计算机中的容错时间同步机制公开(公告)号：US20080244300A1
公开(公告)日：2008-10-02
申请号：US12140028
申请日：2008-06-16
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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3.发明授权Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效可扩展多处理器计算机中的容错时间同步机制的方法和装置公开(公告)号：US07761726B2
公开(公告)日：2010-07-20
申请号：US12116652
申请日：2008-05-07
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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4.发明授权Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 有权可扩展多处理器计算机中的容错时间同步机制的方法和装置公开(公告)号：US07487377B2
公开(公告)日：2009-02-03
申请号：US11054294
申请日：2005-02-09
IPC分类号： G06F13/42
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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5.发明授权Fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效可扩展多处理器计算机中的容错时间同步机制公开(公告)号：US07865758B2
公开(公告)日：2011-01-04
申请号：US12140028
申请日：2008-06-16
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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6.发明授权Method and apparatus for frequency independent processor utilization recording register in a simultaneously multi-threaded processor 有权用于频率独立处理器利用记录寄存器的同时多线程处理器的方法和装置公开(公告)号：US07870406B2
公开(公告)日：2011-01-11
申请号：US11050325
申请日：2005-02-03
IPC分类号： G06F1/00
CPC分类号： G06F11/3442 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F11/3471 , G06F2201/88 , G06F2201/885 , Y02D10/126
摘要： Mechanism for accurately measuring useful capacity of a processor allocated to each thread in a simultaneously multi-threading data processing system. Instructions dispatched from multiple threads are executed by the processor on a same clock cycle. A determination is made whether Time Base (TB) register bit (60) is changing. A dispatch charge value is determined for each thread, and added to the Processor Utilization Resource Register for each thread when TB bit (60) changes.
摘要翻译： 用于准确测量在同时多线程数据处理系统中分配给每个线程的处理器的有用容量的机制。 从多个线程调度的指令由处理器以相同的时钟周期执行。 确定时基（TB）寄存器位（60）是否改变。 为每个线程确定调度费用值，并在TB位（60）更改时将其添加到每个线程的处理器利用资源寄存器中。
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7.发明授权Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor 失效用于减少在多线程处理器中检查点指令所需的周期数的方法和装置公开(公告)号：US07409589B2
公开(公告)日：2008-08-05
申请号：US11140648
申请日：2005-05-27
IPC分类号： G06F11/00
CPC分类号： G06F11/1407
摘要： A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.
摘要翻译： 提供了一种方法和装置，用于减少具有调度组检查点的多线程微处理器中检查点指令所需的周期数。 在检查点流水线的第一阶段中确定是否可以针对一组指令检查点。 处理指令组的结果流到检查点流水线的第二阶段，而不管指令组是否准备好检查点。 如果指令组准备好进行检查点，那么在检查点流水线的第三阶段中，指令组将被检查点。
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8.发明授权Method and apparatus for equalizing grants of a data bus to primary and secondary devices 失效用于将数据总线授予主要和次要设备的方法和装置
公开(公告)号：US5805836A
公开(公告)日：1998-09-08
申请号：US762901
申请日：1996-12-10
IPC分类号： G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
CPC分类号： G06F13/364 , G06F13/4031
摘要： An apparatus for equalizing grants of a primary bus to a plurality of primary devices and secondary devices is provided. The apparatus comprises a primary bus bridge to arbitrate grants of the primary bus among a plurality of primary devices attached to the primary bus and a secondary bus bridge to arbitrate grants of the primary bus among a plurality of secondary devices attached to a secondary bus. A logic device is also provided to equalize grants of the primary bus to the primary and the secondary devices.
摘要翻译： 提供了一种用于将主总线的授权均衡到多个主设备和辅助设备的设备。 该装置包括主总线桥，用于在连接到主总线的多个主设备中仲裁主总线的授权，以及辅助总线桥，用于在附加到辅助总线的多个辅助设备中仲裁主总线的授权。 还提供了一个逻辑设备，用于将主总线的授权与主设备和辅助设备相等。
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