Invention Grant
US07867865B2 Methods of fabricating semiconductor devices including elevated source and drain regions
有权
制造包括升高的源极和漏极区域的半导体器件的方法
- Patent Title: Methods of fabricating semiconductor devices including elevated source and drain regions
- Patent Title (中): 制造包括升高的源极和漏极区域的半导体器件的方法
-
Application No.: US12166575Application Date: 2008-07-02
-
Publication No.: US07867865B2Publication Date: 2011-01-11
- Inventor: Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
- Applicant: Jin-Bum Kim , Young-Pil Kim , Jung-Yun Won , Hion-Suck Baik , Jun-Ho Lee
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec
- Priority: KR10-2007-0066217 20070702
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Methods of fabricating semiconductor devices are provided. A substrate having active patterns and isolating layer patterns is prepared. Each of the isolating layer patterns has an upper surface higher than that of each of the active patterns. A spacer layer having a uniform thickness is formed on the substrate. The spacer layer is etched to form a spacer on a sidewall of each of the isolating layer patterns. A gate structure is formed on each of the active patterns. A selective epitaxial growth (SEG) process is performed on the active patterns having the gate structure to form isolated epitaxial layers that have upper surfaces higher than those of the isolating layer patterns, on the active patterns. Related semiconductor devices are also provided.
Public/Granted literature
- US20090008717A1 Semiconductor Devices Including Elevated Source and Drain Regions and Methods of Fabricating the Same Public/Granted day:2009-01-08
Information query
IPC分类: