发明授权
US07872937B2 Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor 有权
用于动态随机存取存储器(DRAM)控制器等的数据驱动器电路及其方法

Data driver circuit for a dynamic random access memory (DRAM) controller or the like and method therefor
摘要:
A data driver includes a first latch (322), an extension logic circuit (324), and a second latch (330). The first latch (322) has an input for receiving an input data signal, a clock input for receiving a first clock signal, and an output. The extension logic circuit (324) has an input coupled to the output of the first latch (322), a control input for receiving a control signal, and an output. The extension logic circuit (324) selectively delays the output of the first latch (322) in response to the control signal. The second latch (330) has an input coupled to the output of the extension logic circuit (324), a clock input for receiving a second clock signal, and an output for providing an output data signal.
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