发明授权
US07877714B2 System and method to optimize semiconductor power by integration of physical design timing and product performance measurements
有权
通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法
- 专利标题: System and method to optimize semiconductor power by integration of physical design timing and product performance measurements
- 专利标题(中): 通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法
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申请号: US12038320申请日: 2008-02-27
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公开(公告)号: US07877714B2公开(公告)日: 2011-01-25
- 发明人: Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
- 申请人: Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Roberts Mlotkowski Safran & Cole, P.C.
- 代理商 Richard Kotulak
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.