-
1.发明授权System and method to optimize semiconductor power by integration of physical design timing and product performance measurements 有权通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法公开(公告)号：US07877714B2
公开(公告)日：2011-01-25
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。
-
2.发明授权公开(公告)号：US09117045B2
公开(公告)日：2015-08-25
申请号：US12031079
申请日：2008-02-14
CPC分类号： G06F17/505 , G01R31/3008 , G06F17/5068 , H01L22/34
摘要： A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.
摘要翻译： 一种用于预测和控制泄漏的方法，其中将IDDQ预测宏放置在多个设计拓扑中，并且使用IDDQ预测宏来收集数据。 IDDQ预测宏被配置为使用IDDQ预测宏来测量半导体测试位置和划线中的至少一种设备类型的亚阈值泄漏和栅极泄漏并建立泄漏模型。 该方法将半导体测试现场测量和划线测量相关联，以建立划线控制限制，预测产品泄漏; 并使用泄漏模型为每个产品设置亚阈值泄漏限值和门泄漏限值。
-
3.发明申请公开(公告)号：US20090210201A1
公开(公告)日：2009-08-20
申请号：US12031079
申请日：2008-02-14
CPC分类号： G06F17/505 , G01R31/3008 , G06F17/5068 , H01L22/34
摘要： A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.
摘要翻译： 一种用于预测和控制泄漏的方法，其中将IDDQ预测宏放置在多个设计拓扑中，并且使用IDDQ预测宏来收集数据。 IDDQ预测宏被配置为使用IDDQ预测宏来测量半导体测试位置和划线中的至少一种设备类型的亚阈值泄漏和栅极泄漏并建立泄漏模型。 该方法将半导体测试现场测量和划线测量相关联，以建立划线控制限制，预测产品泄漏; 并使用泄漏模型为每个产品设置亚阈值泄漏限值和门泄漏限值。
-
4.发明申请SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS 有权通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法公开(公告)号：US20090217221A1
公开(公告)日：2009-08-27
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. ANEMIKOS , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. ANEMIKOS , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。
-
-
-
搜索结果
4 条记录 (耗时 0.011 秒)