Invention Grant
US07884003B2 Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
有权
在电连接处去除半导体的费米能级的方法以及包含这种结的装置的方法
- Patent Title: Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
- Patent Title (中): 在电连接处去除半导体的费米能级的方法以及包含这种结的装置的方法
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Application No.: US12197996Application Date: 2008-08-25
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Publication No.: US07884003B2Publication Date: 2011-02-08
- Inventor: Daniel E. Grupp , Daniel J. Connelly
- Applicant: Daniel E. Grupp , Daniel J. Connelly
- Applicant Address: US CA Santa Monica
- Assignee: Acorn Technologies, Inc.
- Current Assignee: Acorn Technologies, Inc.
- Current Assignee Address: US CA Santa Monica
- Agency: SNR Denton US LLP
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/44

Abstract:
An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 Ω-μm2 or even less than or equal to 1 Ω-μm2 for the electrical device.
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