Invention Grant
- Patent Title: Semiconductor device and fabrication method thereof
- Patent Title (中): 半导体器件及其制造方法
-
Application No.: US12134516Application Date: 2008-06-06
-
Publication No.: US07884423B2Publication Date: 2011-02-08
- Inventor: Kunihiko Iwamoto , Arito Ogawa , Yuuichi Kamimuta
- Applicant: Kunihiko Iwamoto , Arito Ogawa , Yuuichi Kamimuta
- Applicant Address: JP Kyoto-fu JP Tokyo JP Tokyo
- Assignee: Rohm Co., Ltd.,Hitachi Kokusai Electric Inc.,Kabushiki Kaisha Toshiba
- Current Assignee: Rohm Co., Ltd.,Hitachi Kokusai Electric Inc.,Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Kyoto-fu JP Tokyo JP Tokyo
- Agency: Fish & Richardson P.C.
- Priority: JPP2007-152871 20070608
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/8238

Abstract:
CMISFETs having a symmetrical flat band voltage, the same gate electrode material, and a high permittivity dielectric layer is provided for a semiconductor device including n-MISFETs and p-MISFETs, and a fabrication method thereof, the n-MISFETs including: a first metal oxide layer 20, placed on the 1st gate insulating film 16, having a composition ratio shown with M1xM2yO (where M1=Y, La, Ce, Pr, Nd, Sm, Gd, Th, Dy, Ho, Er, Tm, Yb or Lu, M2=Hf, Zr or Ta, and x/(x+y)>0.12); a second metal oxide layer 24; and a second metal oxide layer 24, the p-MISFETs including: a second gate insulating film 18 placed on the surface of the semiconductor substrate 10; a third metal oxide layer 22, placed on the 2nd gate insulating film 18, having a composition ratio shown with M3zM4wO (M3=Al, M4=Hf, Zr or Ta, and z/(z+w)>0.14); a fourth metal oxide layer 26; and a second conductive layer 30 placed on the fourth metal oxide layer 26.
Public/Granted literature
- US20080303099A1 Semiconductor Device and Fabrication Method Thereof Public/Granted day:2008-12-11
Information query
IPC分类: