发明授权
US07893494B2 Method and structure for SOI body contact FET with reduced parasitic capacitance
有权
具有降低的寄生电容的SOI体接触FET的方法和结构
- 专利标题： Method and structure for SOI body contact FET with reduced parasitic capacitance
- 专利标题（中）： 具有降低的寄生电容的SOI体接触FET的方法和结构
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申请号： US12141276申请日： 2008-06-18
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公开(公告)号： US07893494B2公开(公告)日： 2011-02-22
- 发明人: Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
- 申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Scully, Scott, Murphy & Presser
- 主分类号： H01L27/12
- IPC分类号： H01L27/12
摘要：
In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.