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1.发明申请METHOD AND STRUCTURE FOR SOI BODY CONTACT FET WITH REDUCED PARASITIC CAPACITANCE 有权具有降低PARASITIC电容的SOI体接触FET的方法和结构公开(公告)号：US20090315138A1
公开(公告)日：2009-12-24
申请号：US12141276
申请日：2008-06-18
IPC分类号： H01L27/12 , H01L21/3205
CPC分类号： H01L29/78615 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.
摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。
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2.发明授权Method and structure for SOI body contact FET with reduced parasitic capacitance 有权具有降低的寄生电容的SOI体接触FET的方法和结构公开(公告)号：US07893494B2
公开(公告)日：2011-02-22
申请号：US12141276
申请日：2008-06-18
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.
摘要翻译： 在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。
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3.发明申请FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT 失效具有减少的低温分离分离诱发的漏电流的场效应晶体管公开(公告)号：US20090224335A1
公开(公告)日：2009-09-10
申请号：US12041967
申请日：2008-03-04
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译： 沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。 可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。 可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。 由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。
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4.发明授权Field effect transistor with reduced shallow trench isolation induced leakage current 失效场效应晶体管减少浅沟槽隔离引起的漏电流公开(公告)号：US07804140B2
公开(公告)日：2010-09-28
申请号：US12041967
申请日：2008-03-04
IPC分类号： H01L27/088
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译： 沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。 可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。 可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。 由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。
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公开(公告)号：US20080303105A1
公开(公告)日：2008-12-11
申请号：US11759538
申请日：2007-06-07
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance.
摘要翻译： 提供了包含具有比NFET栅极电介质更厚的有效氧化物厚度（EOT）的PFET栅极电介质的SRAM单元结构及其制造方法。 PFET栅极电介质和NFET栅极电介质可以是氮氧化硅层，CVD氧化物层或具有不同厚度的高K电介质层。 PFET栅极电介质可以是两个电介质层的堆叠，并且NFET栅极电介质可以是两个电介质层中的一个。 PFET栅极电介质的更大的EOT产生上拉PFET的导通电流的降低，以获得最佳的SRAM性能。
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6.发明申请Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS 审中-公开金属高K（MHK）双栅应力工程使用混合方向（HOT）CMOS公开(公告)号：US20100159684A1
公开(公告)日：2010-06-24
申请号：US12706882
申请日：2010-02-17
IPC分类号： H01L21/28
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/665 , H01L29/66545
摘要： A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack.
摘要翻译： 混合取向技术（HOT）CMOS结构由拉伸应力NFET栅极堆叠和压缩应力PFET栅极堆叠构成，其中每个栅极堆叠由高介电常数氧化物/金属组成，并且其中源 拉伸应力NFET栅极堆叠和压应力PFET栅极堆叠是高k金属栅极堆叠中的金属。
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公开(公告)号：US07550337B2
公开(公告)日：2009-06-23
申请号：US11759538
申请日：2007-06-07
IPC分类号： H01L21/8238 , H01L21/336 , G11C16/04
CPC分类号： H01L27/1104 , H01L27/0207 , H01L27/11
摘要： An SRAM cell structure containing a PFET gate dielectric having a thicker effective oxide thickness (EOT) than an NFET gate dielectric and methods of manufacturing the same is provided. The PFET gate dielectric and the NFET gate dielectric may be silicon oxynitride layers, CVD oxide layers, or high-K dielectric layers having different thicknesses. The PFET gate dielectric may be a stack of two dielectric layers and the NFET gate dielectric may be one of the two dielectric layers. The greater EOT of the PFET gate dielectric produces reduction of the on-current of the pull-up PFETs for optimal SRAM performance.
摘要翻译： 提供了包含具有比NFET栅极电介质更厚的有效氧化物厚度（EOT）的PFET栅极电介质的SRAM单元结构及其制造方法。 PFET栅极电介质和NFET栅极电介质可以是氮氧化硅层，CVD氧化物层或具有不同厚度的高K电介质层。 PFET栅极电介质可以是两个电介质层的堆叠，并且NFET栅极电介质可以是两个电介质层中的一个。 PFET栅极电介质的更大的EOT产生上拉PFET的导通电流的降低，以获得最佳的SRAM性能。
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8.发明申请Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS 审中-公开金属高K（MHK）双栅应力工程使用混合方向（HOT）CMOS公开(公告)号：US20090072312A1
公开(公告)日：2009-03-19
申请号：US11855204
申请日：2007-09-14
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1207 , H01L29/665 , H01L29/66545
摘要： A hybrid orientation technology (HOT) CMOS structure is comprised of a tensile stressed NFET gate stack and a compressively stressed PFET gate stack, where each gate stack is comprised of a high dielectric constant oxide/metal, and where the source of the stress in the tensile stressed NFET gate stack and the compressively stressed PFET gate stack is the metal in the high-k metal gate stack.
摘要翻译： 混合取向技术（HOT）CMOS结构由拉伸应力NFET栅极堆叠和压缩应力PFET栅极堆叠构成，其中每个栅极堆叠由高介电常数氧化物/金属组成，并且其中源 拉伸应力NFET栅极堆叠和压应力PFET栅极堆叠是高k金属栅极堆叠中的金属。
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9.发明授权Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池公开(公告)号：US07274072B2
公开(公告)日：2007-09-25
申请号：US11108012
申请日：2005-04-15
IPC分类号： H01L29/72
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。
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10.发明申请Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance 有权用于改善电池稳定性和性能的混合体SOI-6T-SRAM电池公开(公告)号：US20060231899A1
公开(公告)日：2006-10-19
申请号：US11108012
申请日：2005-04-15
IPC分类号： H01L29/94
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/84 , H01L27/11 , H01L27/1203 , H01L27/1207
摘要： The present invention provides a 6T-SRAM semiconducting structure including a substrate having an SOI region and a bulk-Si region, wherein the SOI region and the bulk-Si region have a same or differing crystallographic orientation; an isolation region separating the SOI region from the bulk-Si region; and at least one first device located in the SOI region and at least one second device located in the bulk-Si region. The SOI region has an silicon layer atop an insulating layer. The bulk-Si region further comprises a well region underlying the second device and a contact to the well region, wherein the contact stabilizes floating body effects. The well contact is also used to control the threshold voltages of the FETs in the bulk-Si region to optimized the power and performance of the SRAM cell built from the combination of the SOI and bulk-Si region FETs.
摘要翻译： 本发明提供了一种6T-SRAM半导体结构，其包括具有SOI区域和体积-Si区域的衬底，其中SOI区域和体积-Si区域具有相同或不同的晶体取向; 将SOI区域与体Si区域分离的隔离区域; 以及位于SOI区域中的至少一个第一器件和位于本体Si区域中的至少一个第二器件。 SOI区域在绝缘层顶部具有硅层。 体硅区域还包括位于第二器件下面的阱区域和与阱区域的接触，其中接触稳定浮体效应。 阱接触还用于控制体Si区域中的FET的阈值电压，以优化由SOI和体Si区域FET的组合构建的SRAM单元的功率和性能。
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