发明授权
- 专利标题: System for improving a logic circuit and associated methods
- 专利标题(中): 用于改进逻辑电路和相关方法的系统
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申请号: US11873919申请日: 2007-10-17
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公开(公告)号: US07895539B2公开(公告)日: 2011-02-22
- 发明人: Christopher Carney , Jose Luis Pontes Correia Neves , Biagio Pluchino
- 申请人: Christopher Carney , Jose Luis Pontes Correia Neves , Biagio Pluchino
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 William A. Kinnaman, Jr.
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.