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    System for improving a logic circuit and associated methods
    1.
    发明授权
    System for improving a logic circuit and associated methods 有权
    用于改进逻辑电路和相关方法的系统

    公开(公告)号：US07895539B2

    公开(公告)日：2011-02-22

    申请号：US11873919

    申请日：2007-10-17

    申请人： Christopher Carney ,  Jose Luis Pontes Correia Neves ,  Biagio Pluchino

    发明人： Christopher Carney ,  Jose Luis Pontes Correia Neves ,  Biagio Pluchino

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

    摘要翻译： 用于改进逻辑电路的系统可以包括处理器和与处理器通信以对多个网络建模的逻辑电路分析器。 该系统还可以包括与逻辑电路分析器通信的接口，以针对多个网络中的每一个网络选择目标松弛值。 逻辑电路分析器可以确定每个网络的松弛值。 此外，如果确定的松弛值小于每个相应网的目标松弛值，则逻辑电路分析器可以分别选择性地减小每个网络的电阻 - 电容延迟。

    System for Improving a Logic Circuit and Associated Methods
    2.
    发明申请
    System for Improving a Logic Circuit and Associated Methods 有权
    改进逻辑电路和相关方法的系统

    公开(公告)号：US20090106709A1

    公开(公告)日：2009-04-23

    申请号：US11873919

    申请日：2007-10-17

    申请人： Christopher Carney ,  Jose Luis Neves ,  Biagio Pluchino

    发明人： Christopher Carney ,  Jose Luis Neves ,  Biagio Pluchino

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/505

    摘要： A system for improving a logic circuit may include a processor, and a logic circuit analyzer in communication with the processor to model a plurality of nets. The system may also include an interface in communication with the logic circuit analyzer to select a target slack-value for each one of the plurality of nets. The logic circuit analyzer may determine a slack-value for each net. In addition, the logic circuit analyzer may selectively reduce resistive-capacitive delay for each net respectively if the determined slack-value is less than the target slack-value for each respective net.

    摘要翻译： 用于改进逻辑电路的系统可以包括处理器和与处理器通信以对多个网络建模的逻辑电路分析器。 该系统还可以包括与逻辑电路分析器通信的接口，以针对多个网络中的每一个网络选择目标松弛值。 逻辑电路分析器可以确定每个网络的松弛值。 此外，如果确定的松弛值小于每个相应网的目标松弛值，则逻辑电路分析器可以分别选择性地减小每个网络的电阻 - 电容延迟。