发明授权
US07898286B2 Critical path redundant logic for mitigation of hardware across chip variation
有权
用于缓解跨芯片变化的硬件的关键路径冗余逻辑
- 专利标题: Critical path redundant logic for mitigation of hardware across chip variation
- 专利标题(中): 用于缓解跨芯片变化的硬件的关键路径冗余逻辑
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申请号: US12369066申请日: 2009-02-11
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公开(公告)号: US07898286B2公开(公告)日: 2011-03-01
- 发明人: Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
- 申请人: Igor Arsovski , Hayden C. Cranford, Jr. , Joseph A. Iadanza , Todd E. Leonard , Jason M. Norman , Hemen R. Shah , Sebastian T. Ventrone
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Roberts Mlotkowski Safran & Cole. P.C.
- 代理商 David Cain
- 主分类号: H03K19/00
- IPC分类号: H03K19/00
摘要:
Cross-die connection structure and method for a die or chip includes buffer elements having a buffer driver and bypass, and control lines coupled to the buffer elements in order to select one of the buffer driver and bypass for each respective buffer element. A logic network is arranged with the buffer elements to form functional paths, a test unit is structured and arranged to test the functional paths and to be coupled to the control lines, and a configuration storage register to set the selected one of the buffer driver and bypass for each passing functional path.