A variable frequency clock output circuit, comprising: a target value register which stores a target value corresponding to an arbitrarily set target frequency; an increase/decrease value register which stores an arbitrarily set increase/decrease value; an adder-subtractor which has an input portion into which a current output value is inputted and outputs a calculation result obtained by adding/subtracting the increase/decrease value stored in the increase/decrease value register to/from the current output value inputted into the input portion based on an addition/subtraction instruction signal; a comparator which compares an output value of the adder-subtractor to the target value stored in the target value register, and outputs an addition/subtraction instruction signal to the adder-subtractor until the output value of the adder-subtractor and the target value coincide; and a clock generator which outputs a clock signal having a frequency proportional to the output value of the adder-subtractor.