发明授权
- 专利标题: Forming of the last metallization level of an integrated circuit
- 专利标题(中): 形成集成电路的最后一个金属化水平
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申请号: US10791136申请日: 2004-03-02
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公开(公告)号: US07919864B2公开(公告)日: 2011-04-05
- 发明人: Jacky Seiller , Jean-François Revel , Claude Douce
- 申请人: Jacky Seiller , Jean-François Revel , Claude Douce
- 申请人地址: FR Montrouge
- 专利权人: STMicroelectronics S.A.
- 当前专利权人: STMicroelectronics S.A.
- 当前专利权人地址: FR Montrouge
- 代理机构: Wolf, Greenfield & Sacks, P.C.
- 代理商 Lisa K. Jorgenson; James H. Morris
- 优先权: FR0350672 20031013
- 主分类号: H01L29/40
- IPC分类号: H01L29/40 ; H01L21/4763
摘要:
An integrated circuit including one or several metallization levels, metal conductive strips and metal contact pads being formed on the last metallization level, the last level being covered with a passivation layer in which are formed openings above the contact pads. The thickness of the pads, at least at the level of their portions not covered by the passivation layer, is smaller than the thickness of said conductive strips.
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