发明授权
- 专利标题: Electronic package having stress buffer layer on mounting surface thereof, and method for manufacturing same
- 专利标题(中): 在其安装表面上具有应力缓冲层的电子封装及其制造方法
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申请号: US12851686申请日: 2010-08-06
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公开(公告)号: US07923904B2公开(公告)日: 2011-04-12
- 发明人: Hitoshi Takeuchi , Keiji Sato , Kiyoshi Aratake , Masashi Numata
- 申请人: Hitoshi Takeuchi , Keiji Sato , Kiyoshi Aratake , Masashi Numata
- 申请人地址: JP Chiba
- 专利权人: Seiko Instruments Inc.
- 当前专利权人: Seiko Instruments Inc.
- 当前专利权人地址: JP Chiba
- 代理机构: Brinks Hofer Gilson & Lione
- 优先权: JP2008-032046 20080213
- 主分类号: H01L41/08
- IPC分类号: H01L41/08
摘要:
An electronic component capable of withstanding stress from a printed circuit board or the like is provided. In an electronic component, a cavity hermetically sealed by a base and a lid is formed. In the cavity, a crystal resonator is supported by a supporting member over the top surface of the base. The base is made of glass. A stress buffer layer made of a conductive resin or the like is formed over the whole bottom surface of the base. An external electrode and an external electrode that are in continuity with the electrodes of the crystal resonator individually extend to the bottom surface of the stress buffer layer via the side surfaces of the base and stress buffer layer. The thus configured electronic component is surface-mounted by, for example, soldering the external electrode and external electrode formed on the bottom surface of the stress buffer layer to a printed circuit board.
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