Invention Grant
- Patent Title: Electronic package having stress buffer layer on mounting surface thereof, and method for manufacturing same
- Patent Title (中): 在其安装表面上具有应力缓冲层的电子封装及其制造方法
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Application No.: US12851686Application Date: 2010-08-06
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Publication No.: US07923904B2Publication Date: 2011-04-12
- Inventor: Hitoshi Takeuchi , Keiji Sato , Kiyoshi Aratake , Masashi Numata
- Applicant: Hitoshi Takeuchi , Keiji Sato , Kiyoshi Aratake , Masashi Numata
- Applicant Address: JP Chiba
- Assignee: Seiko Instruments Inc.
- Current Assignee: Seiko Instruments Inc.
- Current Assignee Address: JP Chiba
- Agency: Brinks Hofer Gilson & Lione
- Priority: JP2008-032046 20080213
- Main IPC: H01L41/08
- IPC: H01L41/08

Abstract:
An electronic component capable of withstanding stress from a printed circuit board or the like is provided. In an electronic component, a cavity hermetically sealed by a base and a lid is formed. In the cavity, a crystal resonator is supported by a supporting member over the top surface of the base. The base is made of glass. A stress buffer layer made of a conductive resin or the like is formed over the whole bottom surface of the base. An external electrode and an external electrode that are in continuity with the electrodes of the crystal resonator individually extend to the bottom surface of the stress buffer layer via the side surfaces of the base and stress buffer layer. The thus configured electronic component is surface-mounted by, for example, soldering the external electrode and external electrode formed on the bottom surface of the stress buffer layer to a printed circuit board.
Public/Granted literature
- US20100295421A1 ELECTRONIC COMPONENT, ELECTRONIC APPARATUS, AND BASE MEMBER MANUFACTURING METHOD Public/Granted day:2010-11-25
Information query
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