Invention Grant
- Patent Title: Buffer structure for semiconductor device and methods of fabrication
- Patent Title (中): 半导体器件的缓冲结构和制造方法
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Application No.: US12347883Application Date: 2008-12-31
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Publication No.: US07928468B2Publication Date: 2011-04-19
- Inventor: Prashant Majhi , Jack Kavalieros , Wilman Tsai
- Applicant: Prashant Majhi , Jack Kavalieros , Wilman Tsai
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L33/00
- IPC: H01L33/00

Abstract:
Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
Public/Granted literature
- US20100163848A1 BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION Public/Granted day:2010-07-01
Information query
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