Invention Grant
US07928517B2 High frequency transistor layout for low source drain capacitance 有权
用于低源极漏极电容的高频晶体管布局

  • Patent Title: High frequency transistor layout for low source drain capacitance
  • Patent Title (中): 用于低源极漏极电容的高频晶体管布局
  • Application No.: US11630855
    Application Date: 2005-06-22
  • Publication No.: US07928517B2
    Publication Date: 2011-04-19
  • Inventor: Lukas Frederik Tiemeijer
  • Applicant: Lukas Frederik Tiemeijer
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Priority: EP04102947 20040624
  • International Application: PCT/IB2005/052050 WO 20050622
  • International Announcement: WO2006/000993 WO 20060105
  • Main IPC: H01L27/088
  • IPC: H01L27/088
High frequency transistor layout for low source drain capacitance
Abstract:
An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (110,120,130,140). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.
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