发明授权
- 专利标题: Matrix addressing circuitry and liquid crystal display device using the same
- 专利标题(中): 矩阵寻址电路和使用其的液晶显示装置
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申请号: US11659866申请日: 2005-08-11
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公开(公告)号: US07928948B2公开(公告)日: 2011-04-19
- 发明人: Shuji Hagino , Hidetoshi Watanabe , Akihiro Iwatsu , Keitaro Yamashita
- 申请人: Shuji Hagino , Hidetoshi Watanabe , Akihiro Iwatsu , Keitaro Yamashita
- 申请人地址: HK Shatin
- 专利权人: TPO Hong Kong Holdings Limited Corp.
- 当前专利权人: TPO Hong Kong Holdings Limited Corp.
- 当前专利权人地址: HK Shatin
- 代理机构: Liu & Liu
- 优先权: JP2004-236138 20040813
- 国际申请: PCT/IB2005/052665 WO 20050811
- 国际公布: WO2006/018800 WO 20060223
- 主分类号: G09G3/36
- IPC分类号: G09G3/36
摘要:
The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.
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