公开(公告)号：US20070247478A1

公开(公告)日：2007-10-25

申请号：US11659866

申请日：2005-08-11

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

IPC分类号： G09G5/02

CPC分类号： G09G3/3674 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0213 ,  G09G2310/0224 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2330/021

摘要： The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.

摘要翻译： 本发明旨在在减少功耗的同时防止伪影的发生。 用于交替驱动像素的矩阵寻址方法。 图像的帧周期通过在多个块周期的时间序列上连续排序形成，每个块周期由作为用于对一个像素电压的时间序列应用定时的连续排序的前半部分组成的第一半块组成 或更多的行电极被设置为一个极性，第二半块是用于对要被提供有另一极性的一个或多个行电极的像素电压的时间序列应用定时连续排序的周期。 在第一半块中选择偶数行电极和奇数行电极在显示屏上的排列顺序。 在下半部分中选择与空间相邻的那些。 在一个帧周期期间，前半个块中的行电极选择顺序和第二半块中的行电极选择顺序分别与在另一个帧周期期间的对应的半块中的阶数不同，以便减轻块周期 -base视觉伪影。

公开(公告)号：US07928948B2

公开(公告)日：2011-04-19

申请号：US11659866

申请日：2005-08-11

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Akihiro Iwatsu ,  Keitaro Yamashita

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2310/0213 ,  G09G2310/0224 ,  G09G2320/0209 ,  G09G2320/0233 ,  G09G2330/021

摘要： The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.

摘要翻译： 本发明的目的是在减少功耗的同时防止伪影的发生。 用于交替驱动像素的矩阵寻址方法。 图像的帧周期通过在多个块周期的时间序列上连续排序形成，每个块周期由作为用于对一个像素电压的时间序列应用定时的连续排序的前半部分组成的第一半块组成 或更多的行电极被设置为一个极性，第二半块是用于对要被提供有另一极性的一个或多个行电极的像素电压的时间序列应用定时连续排序的周期。 在第一半块中选择偶数行电极和奇数行电极在显示屏上的排列顺序。 在下半部分中选择与空间相邻的那些。 在一个帧周期期间，前半个块中的行电极选择顺序和第二半块中的行电极选择顺序分别与在另一个帧周期期间的对应的半块中的阶数不同，以便减轻块周期 -base视觉伪影。

公开(公告)号：US08284122B2

公开(公告)日：2012-10-09

申请号：US11920374

申请日：2006-05-09

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Yuko Furui ,  Akihiro Iwatsu

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Yuko Furui ,  Akihiro Iwatsu

IPC分类号： G09G3/20 ,  G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/2044 ,  G09G3/2051 ,  G09G3/3614 ,  G09G3/3696 ,  G09G2310/0213 ,  G09G2310/027 ,  G09G2310/04 ,  G09G2320/0673 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2340/0428

摘要： The invention aims at providing a matrix addressing method and circuitry and display device, which enable power savings without as little degrading the legibility of content of an image as possible. A matrix addressing method for driving pixels arranged over a display area by signals supplied to row electrodes and column electrodes arranged to cross one another. Rich-gray-scale pixel information signals (#0 to #63) are generated in a predetermined number of levels of gray scale according to original pixel information signals, while poor-gray-scale pixel information signals (#0 and #63) are generated in a smaller number of levels of gray scale than the maximum number of levels of gray scale, according to original pixel information signals, and rich-gray-scale pixels driven by the rich-gray-scale pixel information signals (#0 to #63) and poor-gray-scale pixels driven by the poor-gray-scale pixel information signals (#0 and #63) are mixed and coexist discretely in at least a part of the display area in a predetermined mixing pattern to display the same image object in a predetermined mode.

摘要翻译： 本发明旨在提供一种矩阵寻址方法和电路和显示装置，其能够实现功率节省，而不会尽可能地降低图像内容的可读性。 一种矩阵寻址方法，用于通过提供给排列成彼此交叉的行电极和列电极的信号来驱动布置在显示区域上的像素。 根据原始像素信息信号，以预定数量的灰度级产生富灰度级像素信息信号（＃0〜＃63），而灰度级差的像素信息信号（＃0和＃63）为 根据原始像素信息信号产生灰度级比灰度级的最大数量级更少的灰度级，以及由富灰阶像素信息信号（＃0至＃ 63）和由不良灰度像素信息信号（＃0和＃63）驱动的不良灰度像素被混合并以预定混合模式离散地共存在显示区域的至少一部分中以显示相同 图像对象。

公开(公告)号：US20090213042A1

公开(公告)日：2009-08-27

申请号：US11920374

申请日：2006-05-09

申请人： Shuji Hagino ,  Hidetoshi Watanabe ,  Yuko Furui ,  Akihiro Iwatsu

发明人： Shuji Hagino ,  Hidetoshi Watanabe ,  Yuko Furui ,  Akihiro Iwatsu

IPC分类号： G09G3/20

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/2044 ,  G09G3/2051 ,  G09G3/3614 ,  G09G3/3696 ,  G09G2310/0213 ,  G09G2310/027 ,  G09G2310/04 ,  G09G2320/0673 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2340/0428

摘要： The invention aims at providing a matrix addressing method and circuitry and display device, which enable power savings without as little degrading the legibility of content of an image as possible. A matrix addressing method for driving pixels arranged over a display area by signals supplied to row electrodes and column electrodes arranged to cross one another. Rich-gray-scale pixel information signals (#0 to #63) are generated in a predetermined number of levels of gray scale according to original pixel information signals, while poor-gray-scale pixel information signals (#0 and #63) are generated in a smaller number of levels of gray scale than the maximum number of levels of gray scale, according to original pixel information signals, and rich-gray-scale pixels driven by the rich-gray-scale pixel information signals (#0 to #63) and poor-gray-scale pixels driven by the poor-gray-scale pixel information signals (#0 and #63) are mixed and coexist discretely in at least a part of the display area in a predetermined mixing pattern to display the same image object in a predetermined mode.

摘要翻译： 本发明旨在提供一种矩阵寻址方法和电路和显示装置，其能够实现功率节省，而不会尽可能地降低图像内容的可读性。 一种矩阵寻址方法，用于通过提供给排列成彼此交叉的行电极和列电极的信号来驱动布置在显示区域上的像素。 根据原始像素信息信号，以预定数量的灰度级产生富灰度级像素信息信号（＃0〜＃63），而灰度级差的像素信息信号（＃0和＃63）为 根据原始像素信息信号产生灰度级比灰度级的最大数量级更少的灰度级，以及由富灰阶像素信息信号（＃0至＃ 63）和由不良灰度像素信息信号（＃0和＃63）驱动的不良灰度像素被混合并以预定混合模式离散地共存在显示区域的至少一部分中以显示相同 图像对象。

公开(公告)号：US07492360B2

公开(公告)日：2009-02-17

申请号：US10526420

申请日：2003-08-28

申请人： Masakatsu Yamashita ,  Shuji Hagino ,  Masaru Yasui

发明人： Masakatsu Yamashita ,  Shuji Hagino ,  Masaru Yasui

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/0247 ,  G09G2320/029 ,  G09G2320/0626

摘要： An image display device having a voltage supplying device generating a first changing voltage for setting a transistor to an on-state and a second changing voltage for setting a transistor to an off-state to operate so as to establish a first supply mode, a second supply mode and a third supply mode to a plurality of gate buses for determining the corrected common electrode voltage.

摘要翻译： 一种图像显示装置，其具有产生用于将晶体管设置为导通状态的第一变化电压的电压提供装置和用于将晶体管设置为截止状态的第二变化电压，以便建立第一供电模式，第二 供给模式和第三供给模式，以确定校正的公共电极电压。

公开(公告)号：US07158108B2

公开(公告)日：2007-01-02

申请号：US10496552

申请日：2002-11-29

申请人： Shuji Hagino

发明人： Shuji Hagino

IPC分类号： G09G3/36 ,  G09G5/10

CPC分类号： G09G3/2011 ,  G09G3/3696 ,  G09G2330/021

摘要： Column electrode driving circuit for a display device which reduces power consumption arid is capable of gray-scale displaying. The driving circuit include a gray-scale voltage producing system including amplifiers whose inputs are applied with a plurality of gray-scale voltages, respectively, and a selecting system for selecting and outputting any of output signals of the amplifiers for each pixel or each predetermined displayed unit in accordance with an image signal indicative of a gray-scale level for the pixel or displayed unit. The gray-scale voltage producing system causes any amplifiers of the amplifiers, which correspond to a predetermined number of predetermined gray scale levels, to be powered off and causing the other amplifiers to be powered on during a predetermined mode, the selecting system select any of output signals of the amplifiers powered on during the predetermined mode. A further construction based on potential divider circuits is also disclosed.

摘要翻译： 用于降低功耗的显示装置的列电极驱动电路能够进行灰度显示。 驱动电路包括灰度电压产生系统，其包括分别施加有多个灰度电压的放大器，以及用于选择和输出用于每个像素或每个预定显示的放大器的任何输出信号的选择系统 单元，其根据指示像素或显示单元的灰度级的图像信号。 灰度电压产生系统使得对应于预定数量的预定灰度级的放大器的任何放大器被断电并且使得其他放大器在预定模式期间被通电，所述选择系统选择 在预定模式期间放大器通电的输出信号。 还公开了基于分压电路的另外的结构。

公开(公告)号：US08115880B2

公开(公告)日：2012-02-14

申请号：US12426420

申请日：2009-04-20

申请人： Shuji Hagino

发明人： Shuji Hagino

IPC分类号： G02F1/1343

CPC分类号： G09G3/3655 ,  G09G2320/0209

摘要： A liquid crystal display (LCD) panel includes a first substrate, a second substrate, a common electrode driving circuit and a reverse gain circuit. A storage capacitor electrode is disposed on the first substrate. A common electrode is disposed on the second substrate which is disposed oppositely to the first substrate. The common electrode driving circuit is electrically connected with the common electrode and outputs a common voltage level signal to the common electrode. The reverse gain circuit is electrically connected to the storage capacitor electrode through a connecting terminal and outputs a reverse gain voltage signal to the common electrode according to a voltage signal of the storage capacitor electrode.

摘要翻译： 液晶显示器（LCD）面板包括第一基板，第二基板，公共电极驱动电路和反向增益电路。 存储电容器电极设置在第一基板上。 公共电极设置在与第一基板相对设置的第二基板上。 公共电极驱动电路与公共电极电连接，并将公共电压电平信号输出到公共电极。 反向增益电路通过连接端子与辅助电容电极电连接，根据存储电容电极的电压信号，向公共电极输出反向增益电压信号。

公开(公告)号：US20090268115A1

公开(公告)日：2009-10-29

申请号：US12426420

申请日：2009-04-20

申请人： Shuji Hagino

发明人： Shuji Hagino

IPC分类号： G02F1/1343

CPC分类号： G09G3/3655 ,  G09G2320/0209

摘要： A liquid crystal display (LCD) panel includes a first substrate, a second substrate, a common electrode driving circuit and a reverse gain circuit. A storage capacitor electrode is disposed on the first substrate. A common electrode is disposed on the second substrate which is disposed oppositely to the first substrate. The common electrode driving circuit is electrically connected with the common electrode and outputs a common voltage level signal to the common electrode. The reverse gain circuit is electrically connected to the storage capacitor electrode through a connecting terminal and outputs a reverse gain voltage signal to the common electrode according to a voltage signal of the storage capacitor electrode.

摘要翻译： 液晶显示器（LCD）面板包括第一基板，第二基板，公共电极驱动电路和反向增益电路。 存储电容器电极设置在第一基板上。 公共电极设置在与第一基板相对设置的第二基板上。 公共电极驱动电路与公共电极电连接，并将公共电压电平信号输出到公共电极。 反向增益电路通过连接端子与辅助电容电极电连接，根据存储电容电极的电压信号，向公共电极输出反向增益电压信号。

公开(公告)号：US06690345B2

公开(公告)日：2004-02-10

申请号：US10029807

申请日：2001-12-27

申请人： Kenji Hanzawa ,  Shuji Hagino

发明人： Kenji Hanzawa ,  Shuji Hagino

IPC分类号： G09G336

CPC分类号： G09G3/3696 ,  G09G2310/0245 ,  G09G2330/02

摘要： After image is reduced by shortening the erasing time after turnoff of the power supply by providing charge flow paths.

摘要翻译： 通过提供电荷流动路径缩短电源关闭后的擦除时间来减少图像。

公开(公告)号：US20060007193A1

公开(公告)日：2006-01-12

申请号：US10526420

申请日：2003-08-28

申请人： Masakatsu Yamashita ,  Shuji Hagino ,  Masaru Yasui

发明人： Masakatsu Yamashita ,  Shuji Hagino ,  Masaru Yasui

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2320/0219 ,  G09G2320/0247 ,  G09G2320/029 ,  G09G2320/0626

摘要： An object of the invention is to provide a image display device in which the component cost and the equipment cost are reduced and a voltage level of a common electrode is easily adjustable to an optimum level. An image display device comprising a plurality of gate buses (G), a plurality of source buses (S), transistors (TFT) each of which is set to an on-state or an off-state in response to a voltage from a respective one of said gate buses (G) and supplies a voltage from said source bus (S) to a pixel electrode (2a) in said on-state, a common electrode (2c), and a corrected voltage supplying means for supplying a common electrode voltage (Vcom′) which has been corrected by a predetermined amount of correction (ΔVcom) to said common electrode (2c), wherein said corrected voltage supplying means generates a first changing voltage for setting said transistor to said on-state and a second changing voltage for setting said transistor to said off-state to operate so as to establish a first supply mode, a second supply mode and a third supply mode, said first supply mode in which said first changing voltage is supplied to a predetermined number of ones of said plurality of gate buses and said second changing voltage is supplied to remaining ones of said plurality of gate buses, said second supply mode in which said first changing voltage is supplied to a larger number of ones of said plurality of gate buses than said predetermined number of gate buses and said second changing voltage is supplied to remaining ones of said plurality of gate buses, and said third supply mode in which said first changing voltage is supplied to a smaller number of ones of said plurality of gate buses than said predetermined number of gate buses and said second changing voltage is supplied to remaining ones of said plurality of gate buses; and determines the corrected common electrode voltage (Vcom′).