Invention Grant
US07936196B2 First delay locking method, delay-locked loop, and semiconductor memory device including the same
失效
第一延迟锁定方法,延迟锁定环和包括其的半导体存储器件
- Patent Title: First delay locking method, delay-locked loop, and semiconductor memory device including the same
- Patent Title (中): 第一延迟锁定方法,延迟锁定环和包括其的半导体存储器件
-
Application No.: US12716373Application Date: 2010-03-03
-
Publication No.: US07936196B2Publication Date: 2011-05-03
- Inventor: Jun Bae Kim , Chang-Hyun Bae , Jung-Bae Lee
- Applicant: Jun Bae Kim , Chang-Hyun Bae , Jung-Bae Lee
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2009-0018098 20090303
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.
Public/Granted literature
- US20100226188A1 FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME Public/Granted day:2010-09-09
Information query