Invention Grant
US07940550B2 Systems and methods for reducing memory array leakage in high capacity memories by selective biasing
有权
通过选择性偏置来减少高容量存储器中的存储器阵列泄漏的系统和方法
- Patent Title: Systems and methods for reducing memory array leakage in high capacity memories by selective biasing
- Patent Title (中): 通过选择性偏置来减少高容量存储器中的存储器阵列泄漏的系统和方法
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Application No.: US12558816Application Date: 2009-09-14
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Publication No.: US07940550B2Publication Date: 2011-05-10
- Inventor: Niranjan Behera , Deepak Sabharwal , Yong Zhang
- Applicant: Niranjan Behera , Deepak Sabharwal , Yong Zhang
- Applicant Address: US CA Moutain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Moutain View
- Agency: Jones Day
- Agent Brett Lovejoy
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.
Public/Granted literature
- US20110063893A1 SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING Public/Granted day:2011-03-17
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