公开(公告)号：US08546251B1

公开(公告)日：2013-10-01

申请号：US12346866

申请日：2008-12-31

Applicant: Vineet Kumar Sachan ,  Amit Khanuja ,  Deepak Sabharwal

Inventor： Vineet Kumar Sachan ,  Amit Khanuja ,  Deepak Sabharwal

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/11226

Abstract: A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes generating a logic zero at a source of the transistor by electrically connecting the source of the transistor to a ground line with the first conductor. Further, the method includes, programming the read only memory cell to logic zero. A method of manufacturing a read only memory cell includes connecting electrically a drain of the transistor to the bit line with a first conductor and a via. The method also includes, connecting electrically a source of the transistor to the drain with the first conductor. Further, the method includes programming the read only memory cell to logic one.

Abstract translation: 制造只读存储单元的方法包括用第一导体和通孔将晶体管的漏极电连接到位线。 该方法还包括通过将晶体管的源极与第一导体电连接到地线，在晶体管的源极处产生逻辑零。 此外，该方法包括将只读存储器单元编程为逻辑0。 制造只读存储单元的方法包括用第一导体和通孔将晶体管的漏极电连接到位线。 该方法还包括：用第一导体将晶体管的源极电连接到漏极。 此外，该方法包括将只读存储器单元编程为逻辑1。

公开(公告)号：US07940550B2

公开(公告)日：2011-05-10

申请号：US12558816

申请日：2009-09-14

Applicant: Niranjan Behera ,  Deepak Sabharwal ,  Yong Zhang

Inventor： Niranjan Behera ,  Deepak Sabharwal ,  Yong Zhang

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413 ,  G11C2207/2227

Abstract: A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.

Abstract translation: 用于SRAM中的泄漏减少的源极偏置机构，其中SRAM单元被布置成多个扇区。 在待机模式下，多个扇区中的扇区中的SRAM单元被取消选择，并且向多个扇区的SRAM单元提供源极偏置电位。 在工作模式中，提供给多个扇区中选定扇区的SRAM单元的源极偏置电位被去激活，并且读出所选扇区内的物理行中的SRAM单元，而未被选择的扇区中剩余的SRAM单元继续 是源偏颇的。 提供给处于待机模式的SRAM单元的源极偏置电位可以根据控制信号的逻辑状态设置为不同的电压。

公开(公告)号：US07298659B1

公开(公告)日：2007-11-20

申请号：US11147791

申请日：2005-06-07

Applicant: Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Sanjiv Kainth

Inventor： Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Sanjiv Kainth

IPC: G11C29/00

CPC classification number: G11C29/06 ,  G11C11/41 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/0401 ,  G11C2029/1202

Abstract: A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Abstract translation: 描述用于测试用于数据保持故障的易失性存储单元阵列（例如，SRAM）的各个存储单元的方法和系统。 在本发明的一个实施例中，通过一对公共位线连接的相邻存储器单元被写入相对或互补的数据，例如逻辑“0”和逻辑“1”。 接下来，通过对连接两个相邻的存储单元的公共位线进行预充电然后同时断言每个存储单元的字线，对两个存储单元进行应力条件。 最后，读取每个单元格中的数据并将其与在产生应力条件之前写入单元格的数据进行比较。

公开(公告)号：US20070070698A1

公开(公告)日：2007-03-29

申请号：US11385269

申请日：2006-03-21

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C16/04

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with each pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. Likewise, a shared bit line is associated with each pair of adjacent columns, except with respect to the edge columns of the array, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为具有M行和N列的阵列的多个存储单元。 共享源线与每对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 类似地，共享位线与每对相邻列相关联，除了相对于阵列的边缘列，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合 到共享位线。

公开(公告)号：US06853572B1

公开(公告)日：2005-02-08

申请号：US10377845

申请日：2003-02-28

Applicant: Deepak Sabharwal

Inventor： Deepak Sabharwal

IPC: G11C5/06 ,  G11C7/18 ,  G11C16/24

CPC classification number: G11C7/18 ,  G11C16/24

Abstract: Various methods, apparatuses, and systems in which a read only memory is arrayed in a multiple rows and columns. A first column of memory cells is organized into groups of memory cells including a first group of memory cells and a second group of memory cells. A first source line connects to one or more memory cells in the first group of memory cells. The first source line changes its voltage state during a read operation on one or more bit cells in the first group. A second source line connects to one or more memory cells in the second group of memory cells. The second source line maintains its voltage state during the read operation.

Abstract translation: 其中只读存储器以多行和列排列的各种方法，装置和系统。 存储器单元的第一列被组织成包括第一组存储器单元和第二组存储器单元的存储单元组。 第一源极线连接到第一组存储器单元中的一个或多个存储器单元。 在第一组中的一个或多个比特单元的读操作期间，第一源线改变其电压状态。 第二源极线连接到第二组存储器单元中的一个或多个存储器单元。 第二个源极线在读取操作期间保持其电压状态。

公开(公告)号：US20110013444A1

公开(公告)日：2011-01-20

申请号：US12891806

申请日：2010-09-28

Applicant: Vineet Kumar SACHAN ,  Deepak Sabharwal ,  Amit Khanuja

Inventor： Vineet Kumar SACHAN ,  Deepak Sabharwal ,  Amit Khanuja

IPC: G11C17/08

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/0653

Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract translation: 具有最小泄漏的只读存储器（ROM）包括包括第一晶体管的ROM阵列，其中第一晶体管的漏极，源极，栅极和主体电连接到处于空闲状态的逻辑零，以确保零 结和亚阈值漏电流。 第一晶体管的漏极通过第二晶体管电连接到主位线。 第二晶体管包括电连接到第一解码电路的栅极，电连接到主位线的漏极。 第一参考位线电连接到第三晶体管的漏极，其中第三晶体管的栅极电连接到用于产生停止读信号的第二解码电路。 第二参考位线，其通过用于产生停止预充电信号的第一感测单元电连接到第一解码电路。

公开(公告)号：US07376013B2

公开(公告)日：2008-05-20

申请号：US11385269

申请日：2006-03-21

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C11/34

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array having M rows and N columns. A shared source line is associated with each pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. Likewise, a shared bit line is associated with each pair of adjacent columns, except with respect to the edge columns of the array, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为具有M行和N列的阵列的多个存储单元。 共享源线与每对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 类似地，共享位线与每对相邻列相关联，除了相对于阵列的边缘列，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合 到共享位线。

公开(公告)号：US07251186B1

公开(公告)日：2007-07-31

申请号：US11147928

申请日：2005-06-07

Applicant: Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Shreekanth Sampigethaya ,  Sanjiv Kainth

Inventor： Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Shreekanth Sampigethaya ,  Sanjiv Kainth

IPC: G11C7/00

CPC classification number: G11C7/1075

Abstract: A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

Abstract translation: 公开了具有单端口存储器单元阵列的多端口存储器件。 根据本发明的一个实施例，多端口存储器件具有N个存储器端口，并且能够在外部产生的核心时钟信号的单个周期期间执行N个读/写操作的任何组合，而没有 需要任何其他外部产生的时钟信号。

公开(公告)号：US08031542B2

公开(公告)日：2011-10-04

申请号：US12891806

申请日：2010-09-28

Applicant: Vineet Kumar Sachan ,  Deepak Sabharwal ,  Amit Khanuja

Inventor： Vineet Kumar Sachan ,  Deepak Sabharwal ,  Amit Khanuja

IPC: G11C7/00

CPC classification number: H01L29/7436 ,  H01L27/0259 ,  H01L29/0653

Abstract: A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

Abstract translation: 具有最小泄漏的只读存储器（ROM）包括包括第一晶体管的ROM阵列，其中第一晶体管的漏极，源极，栅极和主体电连接到处于空闲状态的逻辑零，以确保零 结和亚阈值漏电流。 第一晶体管的漏极通过第二晶体管电连接到主位线。 第二晶体管包括电连接到第一解码电路的栅极，电连接到主位线的漏极。 第一参考位线电连接到第三晶体管的漏极，其中第三晶体管的栅极电连接到用于产生停止读信号的第二解码电路。 第二参考位线，其通过用于产生停止预充电信号的第一感测单元电连接到第一解码电路。

公开(公告)号：US07692964B1

公开(公告)日：2010-04-06

申请号：US11451043

申请日：2006-06-12

Applicant: Deepak Sabharwal ,  Alexander Shubat

Inventor： Deepak Sabharwal ,  Alexander Shubat

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C11/417

Abstract: A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive thereto, the source-biasing potential provided to the cell is deactivated. Upon completion of reading, the source-biasing potential is re-activated.

Abstract translation: 一种具有用于泄漏减少的源偏置机构的静态随机存取存储器（SRAM）单元。 在待机模式下，取消选择单元格的字线，并向单元提供源偏置电位。 在读取模式中，字线被选择并响应于此，提供给单元的源偏置电位被去激活。 读取完成后，源偏置电位被重新激活。