发明授权
- 专利标题： Arithmetic circuit, arithmetic method, and information processing device
- 专利标题（中）： 算术电路，算术方法和信息处理装置
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申请号： US11864084申请日： 2007-09-28
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公开(公告)号： US07941474B2公开(公告)日： 2011-05-10
- 发明人: Hisashige Ando
- 申请人： Hisashige Ando
- 申请人地址： JP Kawasaki
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JP Kawasaki
- 代理机构： Staas & Halsey LLP
- 优先权： JP2006-346997 20061225
- 主分类号： G06F11/16
- IPC分类号： G06F11/16
摘要：
To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.
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