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公开(公告)号：US06519730B1
公开(公告)日：2003-02-11
申请号：US09527484
申请日：2000-03-16
IPC分类号： G06F1100
CPC分类号： G06F11/1407 , G06F11/1641 , G06F11/165 , G06F11/1658
摘要： Disclosed is a computer in which an error caused by an intermittent failure is corrected by using a misprediction recovery mechanism which performs recovery processing if, after having predicted a branch destination of a branch instruction and speculatively executed an instruction at the predicted branch destination, it turns out that the branch prediction was wrong. The computer includes an error detection mechanism for detecting an error in logic operation of the computer, and an instruction re-execution mechanism for correcting an error caused by an intermittent failure when an error is detected by the error detection mechanism, by restoring the computer, using the misprediction recovery mechanism, to a state that existed before the occurrence of the error, and by re-executing a sequence of instructions including the instruction where the error is detected.
摘要翻译： 公开了一种计算机，其中通过使用执行恢复处理的错误预测恢复机制来校正由间歇性故障引起的误差，如果在预测了分支指令的分支目的地并推测在预测分支目的地执行指令之后，则其转向 分支预测是错误的。 计算机包括用于检测计算机的逻辑运算中的错误的错误检测机构，以及用于当通过错误检测机构检测到错误时校正由间歇性故障引起的错误的指令重新执行机构，通过恢复计算机， 使用错误预测恢复机制，到发生错误之前存在的状态，以及通过重新执行包括检测到错误的指令的指令序列。
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2.发明授权公开(公告)号：US07941474B2
公开(公告)日：2011-05-10
申请号：US11864084
申请日：2007-09-28
申请人： Hisashige Ando
发明人： Hisashige Ando
IPC分类号： G06F11/16
CPC分类号： G06F7/483 , G06F11/1405
摘要： To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.
摘要翻译： 为了提供一种浮点运算电路，用于以较少的电路量有效地破坏具有大数字误差的误差，浮点运算电路包括用于输出第一算术结果的第一运算单元，用于输出第 第二算术结果，以及比较电路，用于将第一和第二算术结果之间的比较以预定比特宽度进行比较。
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公开(公告)号：US07038529B2
公开(公告)日：2006-05-02
申请号：US11068761
申请日：2005-03-02
申请人： Yoshitomo Ozeki , Hisashige Ando
发明人： Yoshitomo Ozeki , Hisashige Ando
IPC分类号： G05F1/10
CPC分类号： G05F1/613
摘要： The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.
摘要翻译： 本发明涉及稳定半导体基板上的电源线的电压的稳压器，旨在提供一种在半导体基板上具有小安装面积的稳压器，能够稳定连接电源的路径的电压 电源和半导体基板。 电压稳定器包括连接到电源线Vdd的监视部分110，其监视电源线Vdd的电位并输出指示监视结果的监视信号;以及第一电流控制部分120，其将来自电源线的电流 Vdd根据监视信号稳定电源线Vdd的电压，能够连续自由地通过电流。
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公开(公告)号：US4969029A
公开(公告)日：1990-11-06
申请号：US47551
申请日：1987-04-27
申请人： Hisashige Ando , Hung C. Lai , John J. Zasio
发明人： Hisashige Ando , Hung C. Lai , John J. Zasio
IPC分类号： H01L23/528 , H01L27/118
CPC分类号： H01L27/11807 , H01L23/528 , H01L2924/0002 , H01L2924/3011 , Y10S257/923
摘要： Integrated circuit formed from a semiconductor body having a rectangular grid pattern formed on the body. The grid pattern is defined by lines extending at right angles to each other along X and Y axes. A plurality of basic cells are provided which have a plurality of active elements therein. Each of the basic cells is selected from a limited number of basic cells of different designs. Each of the basic cells is disposed within a rectangular area no greater than a predetermined size and overlying a plurality of grid lines on both the X and Y axes so that each basic cell overlies a plurlity of intersections of the grid lines which define predetermined grid points. Each basic cell includes a power bus, a ground bus, input leads and an output having a predetermined arrangement with respect to certain grid points. The power bus and ground bus and the input leads and output of each basic cell are connected to the basic cell. Leads are provided for connecting the basic cells to form larger integrated circuit units which are called unit cells. The unit cells are connected to form still larger integrated circuits called a function block (FB).
摘要翻译： 集成电路由形成在主体上的矩形网格图案的半导体主体形成。 网格图案由沿X和Y轴线彼此成直角延伸的线限定。 提供了多个在其中具有多个有源元件的基本单元。 每个基本单元从有限数量的不同设计的基本单元中选择。 每个基本单元被设置在不大于预定尺寸的矩形区域中，并且覆盖X和Y轴上的多个网格线，使得每个基本单元覆盖限定预定网格点的网格线的多个交点 。 每个基本单元包括电源总线，接地总线，输入引线和相对于某些网格点具有预定布置的输出。 电源总线和地线总线以及每个基本单元的输入引脚和输出端连接到基本单元。 提供了用于连接基本单元以形成称为单位单元的较大集成电路单元的引线。 单元电池连接形成称为功能块（FB）的更大的集成电路。
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公开(公告)号：US4091293A
公开(公告)日：1978-05-23
申请号：US750884
申请日：1976-12-15
申请人： Hisashige Ando
发明人： Hisashige Ando
CPC分类号： H03K19/23
摘要： A majority decision logic circuit has an odd number of elementary input signal circuits connected in parallel with a power source, each of the elementary input signal circuits being composed of a pair of P- and N-channel MOS transistors, the drains of the MOS transistors being interconnected to form an output terminal at the connection point and the gates being interconnected to form an input terminal at the connection point, all the output terminals of the elementary input signal circuits being connected together to form the output terminal of the majority decision logic circuit. A majority decision logic circuit has, in addition to the odd number of elementary input signal circuits, a plurality of logic circuits having their output terminals respectively connected to the input terminal of the elementary input signal circuits. A majority decision logic circuit comprises the elementary input signal circuits, the logic circuits and switching circuits, whereby the majority of outputs of a selected odd number of input signal circuits is decided. The abovesaid circuits can be formed with MOS transistors only, and are easily fabricated as an integrated circuit.
摘要翻译： 多数决定逻辑电路具有与电源并联连接的奇数个基本输入信号电路，每个基本输入信号电路由一对P-沟道MOS晶体管和N沟道MOS晶体管构成，MOS晶体管的漏极 互连以在连接点处形成输出端子，并且门互连以在连接点处形成输入端子，基本输入信号电路的所有输出端子连接在一起以形成多数决定逻辑电路的输出端子 。 除了奇数个基本输入信号电路之外，多数决定逻辑电路具有分别连接到基本输入信号电路的输入端的多个逻辑电路。 多数决定逻辑电路包括基本输入信号电路，逻辑电路和开关电路，从而确定所选奇数个输入信号电路的大部分输出。 上述电路可以仅由MOS晶体管形成，并且容易地制造为集成电路。
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公开(公告)号：US4933879A
公开(公告)日：1990-06-12
申请号：US157231
申请日：1988-02-18
IPC分类号： G11C11/401 , G06F12/00 , G06T1/60 , G09G5/02 , G09G5/393
摘要： A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows).times.n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.
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公开(公告)号：US4888584A
公开(公告)日：1989-12-19
申请号：US273676
申请日：1988-11-21
摘要： A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.
摘要翻译： 一种用于位图显示系统的矢量图案处理电路，包括：显示单元，该显示单元具有矩阵形式的多个准区域，每个准区域在所述显示单元的平面中形成，每个形成N×N个点。 该电路包括第一和第二存储器单元，每个存储单元包括以矩阵形式形成的多个字，每个字具有N×N位结构; 对应于显示单元的对角准准区域的第一存储单元中的单词和第二存储单元中的对应于其它对角准准区域的单词; 第一和第二字寄存器单元，每个具有N×N位结构; 数字差分分析器（DDA），响应于沿着主轴的矢量图案的梯度，针对每一个，生成用于处理矢量图案的主轴的第一点数据和垂直于主轴的辅轴的第二点数据 主轴上有N个点。 电路还包括位设置电路，响应于来自DDA的第一和第二点数据，激励字寄存器单元中的一个，并且在每个点数据生成时间中将由点数据定义的位设置为通电字寄存器单元 DDA; 以及存储控制电路，寻址由坐标定义的存储器单元之一中的字的至少一个地址，使得在一个字寄存器单元中设置的数据中的至少一个存储在由该地址定义的字中。
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8.发明申请公开(公告)号：US20080155004A1
公开(公告)日：2008-06-26
申请号：US11864084
申请日：2007-09-28
申请人： Hisashige ANDO
发明人： Hisashige ANDO
IPC分类号： G06F7/02
CPC分类号： G06F7/483 , G06F11/1405
摘要： To provide a floating point arithmetic circuit for efficiently defecting an error, which has a large numerical error, with a less circuit amount, the floating point arithmetic circuit comprises a first arithmetic unit for outputting a first arithmetic result, a second arithmetic unit for outputting a second arithmetic result, and a comparison circuit for making a comparison between the first and the second arithmetic results by a predetermined bit width.
摘要翻译： 为了提供一种浮点运算电路，用于以较少的电路量有效地破坏具有大数字误差的误差，浮点运算电路包括用于输出第一算术结果的第一运算单元，用于输出第 第二算术结果，以及比较电路，用于将第一和第二算术结果之间的比较以预定比特宽度进行比较。
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公开(公告)号：US20050146378A1
公开(公告)日：2005-07-07
申请号：US11068761
申请日：2005-03-02
申请人： Yoshitomo Ozeki , Hisashige Ando
发明人： Yoshitomo Ozeki , Hisashige Ando
CPC分类号： G05F1/613
摘要： The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.
摘要翻译： 本发明涉及稳定半导体基板上的电源线的电压的稳压器，旨在提供一种在半导体基板上具有小安装面积的稳压器，能够稳定连接电源的路径的电压 电源和半导体基板。 电压稳定器包括连接到电源线Vdd的监视部分110，其监视电源线Vdd的电位并输出指示监视结果的监视信号;以及第一电流控制部分120，其将来自电源线的电流 Vdd根据监视信号稳定电源线Vdd的电压，能够连续自由地通过电流。
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公开(公告)号：US4162540A
公开(公告)日：1979-07-24
申请号：US887954
申请日：1978-03-20
申请人： Hisashige Ando
发明人： Hisashige Ando
IPC分类号： G11C11/41 , G11C11/4076 , G11C11/409 , G11C11/4091 , G11C11/412 , G11C11/419 , G11C7/00 , G11C7/06
CPC分类号： G11C11/412 , G11C11/4076 , G11C11/409 , G11C11/4091
摘要： A clocked memory comprising a memory matrix having a plurality of memory cells arranged in rows and columns on a semiconductor substrate; a plurality of word select lines in said memory matrix, a plurality of bit lines crossing said select lines and connecting to said memory cells in each column; a drive circuit for driving said word select lines; a plurality of presence amplifiers connected to said bit lines; and a sense clock line parallel to said word select lines and connected to a gate of a transistor in said presence amplifier; and a presense drive circuit connected to said sense clock line and operated by a clock signal, said presense drive circuit having a transistor with controlled charging capability so as to conduct said transistor responsive to the charge of the memory cell in said each column.
摘要翻译： 一种时钟存储器，包括：存储器矩阵，具有在半导体衬底上以行和列排列的多个存储单元; 所述存储器矩阵中的多个字选择线，与所述选择线交叉并连接到每列中的所述存储单元的多个位线; 用于驱动所述字选择线的驱动电路; 连接到所述位线的多个存在放大器; 以及与所述字选择线并联并连接到所述存在放大器中的晶体管的栅极的感测时钟线; 以及连接到所述感测时钟线并由时钟信号操作的预驱动电路，所述预驱动电路具有具有受控充电能力的晶体管，以响应于所述每列中的存储单元的电荷导通所述晶体管。
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