Invention Grant
US07944238B2 (N+1) input flip-flop packing with logic in FPGA architectures
有权
（N + 1）输入触发器封装，具有FPGA架构中的逻辑
- Patent Title: (N+1) input flip-flop packing with logic in FPGA architectures
- Patent Title (中): （N + 1）输入触发器封装，具有FPGA架构中的逻辑
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Application No.: US12717315Application Date: 2010-03-04
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Publication No.: US07944238B2Publication Date: 2011-05-17
- Inventor: Sinan Kaptanoglu
- Applicant: Sinan Kaptanoglu
- Applicant Address: US CA Mountain View
- Assignee: Actel Corporation
- Current Assignee: Actel Corporation
- Current Assignee Address: US CA Mountain View
- Agency: Lewis and Roca LLP
- Main IPC: G06F7/38
- IPC: G06F7/38 ; H03K19/177
Abstract:
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
Public/Granted literature
- US20100156460A1 (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES Public/Granted day:2010-06-24
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