发明授权
US07944238B2 (N+1) input flip-flop packing with logic in FPGA architectures
有权
（N + 1）输入触发器封装，具有FPGA架构中的逻辑
- 专利标题： (N+1) input flip-flop packing with logic in FPGA architectures
- 专利标题（中）： （N + 1）输入触发器封装，具有FPGA架构中的逻辑
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申请号： US12717315申请日： 2010-03-04
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公开(公告)号： US07944238B2公开(公告)日： 2011-05-17
- 发明人: Sinan Kaptanoglu
- 申请人： Sinan Kaptanoglu
- 申请人地址： US CA Mountain View
- 专利权人： Actel Corporation
- 当前专利权人： Actel Corporation
- 当前专利权人地址： US CA Mountain View
- 代理机构： Lewis and Roca LLP
- 主分类号： G06F7/38
- IPC分类号： G06F7/38 ; H03K19/177
摘要：
A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
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