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发明授权
US07953933B1 Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit 有权
指令缓存，解码电路，基本块高速缓存电路和多块高速缓存电路

Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit
摘要：
An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a basic block sequence of at least one of the operations. The basic block sequence is derived from at least one of the decoder sequences and includes at most one conditional control transfer operation. The circuit includes a multi-block cache that includes a multi-block sequence consisting of at least one of the operations derived from two or more smaller op sequences. A sequencer is configured to generate a prediction for the result of a conditional control transfer operation, select the next sequence of operations, and provide an indication of the next sequence to the instructions cache, the basic block cache, and the multi-block cache.
摘要（中）：

指令处理电路包括指令高速缓存器，被配置为接收至少一个指令并且基于此产生至少一个操作的解码器序列的解码器。 该电路包括基本块高速缓存，其包括至少一个操作的基本块序列。 基本块序列从解码器序列中的至少一个导出，并且至多包括一个条件控制传送操作。 该电路包括多块高速缓存，其包括由至少一个从两个或多个较小的操作序列导出的操作中的至少一个的多块序列。 定序器被配置为生成条件控制传送操作的结果的预测，选择下一个操作序列，并且向指令高速缓存，基本块高速缓存和多块高速缓存提供下一个序列的指示。

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