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1.发明授权Promoting and appending traces in an instruction processing circuit based upon a bias value 有权基于偏置值在指令处理电路中促进和追加迹线公开(公告)号：US07814298B1
公开(公告)日：2010-10-12
申请号：US11941883
申请日：2007-11-16
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , Y02D10/13
摘要： A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoting the current trace and the next trace if the current trace is promotable and the next trace is appendable.
摘要翻译： 公开了一种用于促进指令处理电路中的迹线的方法，系统和计算机程序产品。 它们包括确定当前跟踪是否可提升，并确定下一个跟踪是否可附加到当前跟踪。 它们包括在当前跟踪是可升级的并且下一个跟踪是可附加的情况下促进当前跟踪和下一个跟踪。
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2.发明授权Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit 有权指令缓存，解码电路，基本块高速缓存电路和多块高速缓存电路公开(公告)号：US07953933B1
公开(公告)日：2011-05-31
申请号：US11880875
申请日：2007-07-23
IPC分类号： G06F13/00
CPC分类号： G06F9/30061 , G06F9/3802 , G06F9/3808 , G06F9/3836
摘要： An instruction processing circuit includes an instruction cache, a decoder configured to receive at least one of the instructions and to generate, based thereon, a decoder sequence of at least one operation. The circuit includes a basic block cache that includes a basic block sequence of at least one of the operations. The basic block sequence is derived from at least one of the decoder sequences and includes at most one conditional control transfer operation. The circuit includes a multi-block cache that includes a multi-block sequence consisting of at least one of the operations derived from two or more smaller op sequences. A sequencer is configured to generate a prediction for the result of a conditional control transfer operation, select the next sequence of operations, and provide an indication of the next sequence to the instructions cache, the basic block cache, and the multi-block cache.
摘要翻译： 指令处理电路包括指令高速缓存器，被配置为接收至少一个指令并且基于此产生至少一个操作的解码器序列的解码器。 该电路包括基本块高速缓存，其包括至少一个操作的基本块序列。 基本块序列从解码器序列中的至少一个导出，并且至多包括一个条件控制传送操作。 该电路包括多块高速缓存，其包括由至少一个从两个或多个较小的操作序列导出的操作中的至少一个的多块序列。 定序器被配置为生成条件控制传送操作的结果的预测，选择下一个操作序列，并且向指令高速缓存，基本块高速缓存和多块高速缓存提供下一个序列的指示。
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3.发明授权公开(公告)号：US07546420B1
公开(公告)日：2009-06-09
申请号：US11535971
申请日：2006-09-27
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： Efficient trace cache management during self-modifying code processing enables selective invalidation of entries of the trace cache, advantageously retaining some of the entries in the trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. One or more translation ages are associated with each trace cache entry, and are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein are processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented.
摘要翻译： 在自修改代码处理期间，高效的跟踪缓存管理使得能够选择性地使跟踪高速缓存的条目无效，即使在自修改代码事件期间，也有利地保留跟踪高速缓存中的一些条目。 监控底层跟踪缓存条目的指令以进行组中的修改，从而有利于减少硬件。 一个或多个翻译年龄与每个跟踪高速缓存条目相关联，并且通过对入口下面的存储器块的当前年龄进行抽样构建该条目来确定。 当访问条目并处理其中的微操作时，将访问条目的翻译年龄与访问条目下面的存储块的当前年龄进行比较。 如果任何年龄比较失败，则微操作将中止，并且条目无效。 当存储器块的任何部分被修改时，修改的存储器块的当前时间增加。
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4.发明授权Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit 有权用于在指令处理电路中利用公共结构进行跟踪验证和维持一致性的方法和系统公开(公告)号：US08015359B1
公开(公告)日：2011-09-06
申请号：US11782238
申请日：2007-07-24
IPC分类号： G06F13/00
CPC分类号： G06F12/0815 , G06F9/3017 , G06F9/322 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F9/3844 , G06F12/0875 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit for a processor is disclosed. The instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution unit of the processor. The instruction processing circuit comprises at least one cache circuit and the processing circuit includes a sequencer and a page translation buffer coupled to the sequencer for trace verification and maintaining coherency between a memory and the at least one cache.
摘要翻译： 公开了一种用于处理器的指令处理电路。 指令处理电路适于基于一个或多个指令序列向处理器的执行单元提供一个或多个操作序列。 所述指令处理电路包括至少一个高速缓存电路，并且所述处理电路包括定序器和耦合到所述定序器的页面翻译缓冲器，用于跟踪验证并维持存储器与所述至少一个高速缓存之间的一致性。
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5.发明授权Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer 有权具有解码器，基本块高速缓存，多块缓存和定序器的跟踪单元公开(公告)号：US07987342B1
公开(公告)日：2011-07-26
申请号：US11880862
申请日：2007-07-23
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30054 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing circuit includes a cache circuit operable to store a second type of sequence of operations that represents at least a portion of a first type of sequence of operations, where the sequence of operations of the second type includes at most one control transfer that, when present, ends a first portion of a sequence of instructions, where the cache circuit is further configured to store a third type of sequence of operations that represents a set of at least two sequences of operations.
摘要翻译： 一种用于处理器的指令处理电路，其中所述指令处理电路适于基于一个或多个指令序列向所述处理器的执行电路提供一个或多个操作序列。 指令处理电路包括高速缓存电路，其可操作以存储表示第一类型操作序列的至少一部分的第二类型的操作序列，其中第二类型的操作序列包括至多一个控制传输， 当存在时，结束指令序列的第一部分，其中高速缓存电路被进一步配置为存储表示至少两个操作序列的集合的第三类操作序列。
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6.发明授权Selective trace cache invalidation for self-modifying code via memory aging 有权通过内存老化自动修改代码的选择性跟踪缓存无效公开(公告)号：US07676634B1
公开(公告)日：2010-03-09
申请号：US11535972
申请日：2006-09-27
IPC分类号： G06F13/00
CPC分类号： G06F12/0875 , G06F9/30174 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： Selective trace cache invalidation for self-modifying code via memory aging advantageously retains some of the entries in a trace cache even during self-modifying code events. Instructions underlying trace cache entries are monitored for modification in groups, enabling advantageously reduced hardware. Associated with each trace cache entry are translation ages that are determined when the entry is built by sampling current ages of memory blocks underlying the entry. When the entry is accessed and micro-operations therein processed, the translation ages of the accessed entry are compared with the current ages of the memory blocks underlying the accessed entry. If any of the age comparisons fail, then the micro-operations are aborted and the entry is invalidated. When any portion of a memory block is modified, the current age of the modified memory block is incremented. If one of the current ages overflows, then the entire trace cache is flushed.
摘要翻译： 通过内存老化对自修改代码的选择性跟踪高速缓存无效即使在自修改代码事件期间也有助于保留跟踪缓存中的一些条目。 监控底层跟踪缓存条目的指令以进行组中的修改，从而有利于减少硬件。 与每个跟踪缓存条目相关联的是通过对入口底层的内存块的当前年龄进行抽样来构建条目时确定的翻译年龄。 当访问该条目并处理其中的微操作时，将所访问的条目的翻译年龄与所访问的条目下的存储块的当前年龄进行比较。 如果任何年龄比较失败，则微操作将中止，并且条目无效。 当存储器块的任何部分被修改时，修改的存储器块的当前时间增加。 如果当前年龄之一溢出，则整个跟踪缓存将被刷新。
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公开(公告)号：US08037285B1
公开(公告)日：2011-10-11
申请号：US11880882
申请日：2007-07-23
申请人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
发明人： Richard Win Thaik , John Gregory Favor , Joseph Byron Rowlands , Leonard Eric Shar , Matthew William Ashcraft , Ivan Pavle Radivojevic
IPC分类号： G06F15/00
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054 , Y02D10/13
摘要： An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a portion of the sequence of operations of the first type and to generate, based thereon, a second type of sequence of operations, where the at least a portion of the sequence of operations of the first type represents a first portion of the sequence of instructions, where the first portion of the sequence of instructions includes at most one conditional control transfer instruction that, when present, ends the first portion of the sequence of instructions, and where the sequence of operations of the second type also represents the first portion of the sequence of instructions.
摘要翻译： 指令处理电路包括解码器电路，其可操作以接收指令序列并且将接收的指令序列解码为第一类型的操作序列，以及跟踪构建器电路，其可操作以接收至少一部分操作序列 第一类型并基于此产生第二类型的操作序列，其中第一类型的操作序列的至少一部分表示指令序列的第一部分，其中序列的第一部分 指令包括最多一个条件控制传输指令，当存在时，结束指令序列的第一部分，并且第二类型的操作序列也表示指令序列的第一部分。
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公开(公告)号：US07966479B1
公开(公告)日：2011-06-21
申请号：US11880859
申请日：2007-07-23
IPC分类号： G06F9/30
CPC分类号： G06F12/0875 , G06F9/3017 , G06F9/30189 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/1027 , G06F12/1054
摘要： An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.
摘要翻译： 指令处理电路包括解码器电路，基本块构建器电路，多块构建器电路，第一和第二预测器电路和定序器电路，其中定序器电路在第一环境中可操作以使第一预测器 电路，用于与第二预测器电路同时产生用于特定条件分支运算的预测，以产生另一特定条件分支op的预测，其中定序器电路在第二环境中也可操作，以使第一预测电路产生预测 对于特定条件分支，顺序地与第二预测器电路产生对另一特定条件分支操作的预测。
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9.发明授权Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder 有权跟踪单元，具有来自解码器（旁路模式）和基本块构建器的操作路径公开(公告)号：US07953961B1
公开(公告)日：2011-05-31
申请号：US11880863
申请日：2007-07-23
IPC分类号： G06F9/40
CPC分类号： G06F9/30061 , G06F9/3802 , G06F9/3808 , G06F9/3836
摘要： An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution circuit, receive an indication that a sequencing action of the sequencer circuit is sequencing ahead of the execution circuit, and switch, based on the indication, a source of the operations fetch circuit between the cache circuit and the decoder circuit.
摘要翻译： 用于处理器的指令处理电路包括解码器电路，高速缓存电路，可操作以选择下一个操作序列的定序器电路，以及可操作以将下一个操作序列传送到执行电路的操作提取电路，接收指示 定序器电路的排序动作在执行电路之前排序，并且基于指示，在高速缓存电路和解码器电路之间切换操作提取电路的源。
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公开(公告)号：US07949854B1
公开(公告)日：2011-05-24
申请号：US11880861
申请日：2007-07-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30189 , G06F9/3808 , G06F9/3812 , G06F9/3836 , G06F12/0875 , G06F12/1027 , G06F12/1054
摘要： An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one control transfer instruction that, when present, ends the portion, (ii) receive sets of at least two sequences of operations and to generate, based thereon, a plurality of third type of sequences of operations, where a sequence of operations of the third type includes one or more interior control transfer instructions and is generated from the sequence of operations of the second type and another sequence of operations of the third type, and (iii) retrieve the sequence of operations of the second type and the another sequence of operations of the third type from a cache circuit.
摘要翻译： 指令处理单元包括跟踪构建器电路，其可操作以（i）接收第一类型的操作序列的至少一部分并且基于此产生第二类型的操作序列，其中该部分至多包括一个控制 传送指令，当存在时结束部分，（ii）接收至少两个操作序列的集合，并且基于此生成多个第三类型的操作序列，其中第三类型的操作序列包括 一个或多个内部控制传送指令，并且从第二类型的操作序列和第三类型的另一操作序列生成，以及（iii）检索第二类型的操作序列和第二类操作的另一操作序列 第三种类型从缓存电路。
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