发明授权
US07956404B2 Non-volatile two-transistor programmable logic cell and array layout
失效
非易失性双晶体管可编程逻辑单元和阵列布局
- 专利标题： Non-volatile two-transistor programmable logic cell and array layout
- 专利标题（中）： 非易失性双晶体管可编程逻辑单元和阵列布局
-
申请号： US12370828申请日： 2009-02-13
-
公开(公告)号： US07956404B2公开(公告)日： 2011-06-07
- 发明人: Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
- 申请人： Fethi Dhaoui , John McCollum , Vidyadhara Bellippady , William C. Plants , Zhigang Wang
- 申请人地址： US CA Mountain View
- 专利权人： Actel Corporation
- 当前专利权人： Actel Corporation
- 当前专利权人地址： US CA Mountain View
- 代理机构： Lewis and Roca LLP
- 主分类号： H01L29/788
- IPC分类号： H01L29/788
摘要：
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
公开/授权文献
信息查询
IPC分类:
