Invention Grant
US07965098B2 Hardened current mode logic (CML) voter circuit, system and method
有权
硬化电流模式逻辑(CML)选举电路,系统和方法
- Patent Title: Hardened current mode logic (CML) voter circuit, system and method
- Patent Title (中): 硬化电流模式逻辑(CML)选举电路,系统和方法
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Application No.: US12595865Application Date: 2008-12-10
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Publication No.: US07965098B2Publication Date: 2011-06-21
- Inventor: Neil Wood , David Rea , Bin Li
- Applicant: Neil Wood , David Rea , Bin Li
- Applicant Address: US NH Nashua
- Assignee: BAE Systems Information and Electronic Systems Integration Inc.
- Current Assignee: BAE Systems Information and Electronic Systems Integration Inc.
- Current Assignee Address: US NH Nashua
- Agency: Graybeal Jackson LLP
- Agent Paul F. Rusyn
- International Application: PCT/US2008/086291 WO 20081210
- International Announcement: WO2009/076476 WO 20090618
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K19/096 ; H03L7/00

Abstract:
A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.
Public/Granted literature
- US20100141296A1 HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD Public/Granted day:2010-06-10
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