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US07965098B2 Hardened current mode logic (CML) voter circuit, system and method 有权
硬化电流模式逻辑(CML)选举电路,系统和方法

Hardened current mode logic (CML) voter circuit, system and method
Abstract:
A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.
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