Invention Grant
- Patent Title: Method and system for estimating power consumption of integrated circuit design
- Patent Title (中): 集成电路设计功耗估算方法及系统
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Application No.: US12013478Application Date: 2008-01-14
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Publication No.: US07971082B2Publication Date: 2011-06-28
- Inventor: Ashish Mathur , Vijay Bhargava
- Applicant: Ashish Mathur , Vijay Bhargava
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Priority: IN192/DEL/2007 20070131
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.
Public/Granted literature
- US20080184049A1 METHOD AND SYSTEM FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUIT DESIGN Public/Granted day:2008-07-31
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