发明授权
- 专利标题： Configuration interface to stacked FPGA
- 专利标题（中）： 配置接口堆叠FPGA
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申请号： US12128459申请日： 2008-05-28
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公开(公告)号： US07973555B1公开(公告)日： 2011-07-05
- 发明人: Stephen M. Trimberger , Arifur Rahman
- 申请人： Stephen M. Trimberger , Arifur Rahman
- 申请人地址： US CA San Jose
- 专利权人： Xilinx, Inc.
- 当前专利权人： Xilinx, Inc.
- 当前专利权人地址： US CA San Jose
- 代理商 Scott Hewett; LeRoy D. Maunu; Lois D. Cartier
- 主分类号： H03K19/173
- IPC分类号： H03K19/173 ; G06F7/38
摘要：
A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.
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