A digital PLL frequency synthesizer characterized by fast-locking and low-jitters is presented. The PLL comprises a phase detector, a controllable oscillator, a loop filter having an automatically-adjusted loop gain, a feedback phase integration circuit, and a reference phase integration circuit. Fast-locking is achieved by dynamically adjusting forward-path gain and integral-path gain according to the output of the phase detector and the output of the integral-path during phase tracking. A skew-compensated counter circuit is proposed, which incorporates an asynchronous counter, a data register and a sample phase generator and features high-speed and low-power operation.